Patent application number | Description | Published |
20080237777 | Completely decoupled high voltage and low voltage transistor manufacurting processes - A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer. | 10-02-2008 |
20080296673 | Double gate manufactured with locos techniques - This invention discloses a trenched semiconductor power device that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments with a bottom insulation layer surrounding a bottom trench-filling segment having a bird-beak shaped layer on a top portion of the bottom insulation attached to sidewalls of the trench extending above a top surface of the bottom trench-filling segment. | 12-04-2008 |
20100015770 | Double gate manufactured with locos techniques - This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench. | 01-21-2010 |
20110092035 | Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process - A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer. | 04-21-2011 |
20110124167 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions - A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides. | 05-26-2011 |
20120028427 | Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET - This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate. | 02-02-2012 |
20120083084 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source - A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. | 04-05-2012 |
20120129306 | CONFIGURATION AND METHOD TO FORM MOSFET DEVICES WITH LOW RESISTANCE SILICIDE GATE AND MESA CONTACT REGIONS - A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers. | 05-24-2012 |
20120273879 | TOP DRAIN LDMOS - In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate. | 11-01-2012 |