Patent application number | Description | Published |
20100140788 | MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump. | 06-10-2010 |
20100167471 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 07-01-2010 |
20100187651 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit. | 07-29-2010 |
20110156239 | METHOD FOR MANUFACTURING A FAN-OUT EMBEDDED PANEL LEVEL PACKAGE - A method for manufacturing a fan-out embedded panel-level package. Film having an adhesive on each side is applied to the non-active face of a plurality of semiconductor die while the die are still in wafer form. The die are singulated from the wafer and placed on a carrier, using the adhesive on the unused side of the film to attach the die to the carrier. Encapsulant material is dispensed onto the carrier adjacent to the die, providing an exposed surface on the encapsulant material approximately even with the active faces of the die. Elements of the redistribution layer such as conductors and fan-out pads are applied to this surface. A solder ball array is placed on the fan-out pads and then the die are re-singulated by cutting through the encapsulation material and the carrier, yielding individual electronic packages. | 06-30-2011 |
20120038043 | MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump. | 02-16-2012 |
20120098104 | SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT - Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches. | 04-26-2012 |
20120161319 | BALL GRID ARRAY METHOD AND STRUCTURE - A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing. | 06-28-2012 |
20120161332 | METHOD FOR PRODUCING VIAS IN FAN-OUT WAFERS USING DRY FILM AND CONDUCTIVE PASTE, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures. | 06-28-2012 |
20120168938 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice. | 07-05-2012 |
20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168943 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package. | 07-05-2012 |
20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120171875 | RECONSTITUTED WAFER WARPAGE ADJUSTMENT - A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures. | 07-05-2012 |
20120244664 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 09-27-2012 |
20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
20130062764 | SEMICONDUCTOR PACKAGE WITH IMPROVED PILLAR BUMP PROCESS AND STRUCTURE - A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars. | 03-14-2013 |
20130105973 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105982 | LAND GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105991 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130119282 | WAFER LEVEL PACKAGING, OPTICAL DETECTION SENSOR AND METHOD OF FORMING SAME - An optical detection sensor and method of forming same. The optical detection sensor be a proximity detection sensor that includes an optical system and a selectively transmissive structure. Electromagnetic radiation such as laser light can be emitted through a transmissive portion of the selectively transmissive structure. A reflected beam can be detected to determine the presence of an object. | 05-16-2013 |
20130168858 | EMBEDDED WAFER LEVEL BALL GRID ARRAY BAR SYSTEMS AND METHODS - A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package. | 07-04-2013 |
20130171816 | APPARATUS AND METHOD FOR PLACING SOLDER BALLS - A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer. | 07-04-2013 |
20140057394 | METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE - A manufacturing process includes forming a reconstituted wafer, including embedding semiconductor dice in a molding compound layer and forming through-wafer vias in the layer. A fan-out redistribution layer is formed on a front side of the wafer, with electrical traces interconnecting the dice, through-wafer vias, and contact pads positioned on the redistribution layer. Solder balls are positioned on the contact pads and a molding compound layer is formed on the redistribution layer, reinforcing the solder balls. A second fan-out redistribution layer is formed on a back side of the wafer, with electrical traces interconnecting back ends of the through-wafer vias and contact pads positioned on a back face of the second redistribution layer. Flip-chips and/or surface-mounted devices are coupled to the contact pads of the second redistribution layer and encapsulated in an underfill layer formed on the back face of the second redistribution layer. | 02-27-2014 |
20140103476 | METHOD FOR MAKING IMAGE SENSORS USING WAFER-LEVEL PROCESSING AND ASSOCIATED DEVICES - A method of making image sensor devices may include forming a sensor layer including image sensor ICs in an encapsulation material, bonding a spacer layer to the sensor layer, the spacer layer having openings therein and aligned with the image sensor ICs, and bonding a lens layer to the spacer layer, the lens layer including lens in an encapsulation material and aligned with the openings and the image sensor ICs. The method may also include dicing the bonded-together sensor, spacer and lens layers to provide the image sensor devices. Helpfully, the method may use WLP to enhance production. | 04-17-2014 |
20140103521 | ELECTRONIC DEVICE HAVING A CONTACT RECESS AND RELATED METHODS - An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material. | 04-17-2014 |
20140110565 | IMAGE SENSOR DEVICE WITH IR FILTER AND RELATED METHODS - An image sensor device may include a bottom interconnect layer, an image sensing IC above the bottom interconnect layer and coupled thereto, and an adhesive material on the image sensing IC. The image sensor device may include an IR filter layer above the lens layer, and an encapsulation material on the bottom interconnect layer and surrounding the image sensing IC, the lens layer, and the IR filter layer. The image sensor device may include a top contact layer above the encapsulation material and including a dielectric layer, and a contact thereon, the dielectric layer being flush with adjacent portions of the IR filter layer. | 04-24-2014 |
20140175649 | ELECTRONIC DEVICE INCLUDING ELECTRICALLY CONDUCTIVE VIAS HAVING DIFFERENT CROSS-SECTIONAL AREAS AND RELATED METHODS - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via. | 06-26-2014 |
20140191387 | METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE - A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board. | 07-10-2014 |
20140353788 | SEMICONDUCTOR OPTICAL PACKAGE AND METHOD - Embodiments of the present disclosure are directed to optical packages having a package body that includes a light protection coating on at least one surface of a transparent material. The light protection coating includes one or more openings to allow light to be transmitted to the optical device within the package body. In one embodiment, the light protection coating and the openings allow substantially perpendicular radiation to be directed to the optical device within the package body. In one exemplary embodiment the light protection coating is located on an outer surface of the transparent material. In another embodiment, the light protection coating is located on an inner surface of the transparent material inside of the package body. | 12-04-2014 |
20150028187 | IMAGE SENSOR DEVICE WITH INFRARED FILTER ADHESIVELY SECURED TO IMAGE SENSOR INTEGRATED CIRCUIT AND RELATED METHODS - An image sensor device may include a mounting substrate having an IC-receiving cavity therein and a filter-receiving opening aligned with the IC-receiving cavity, an image sensor integrated circuit (IC) within the IC-receiving cavity and having an image sensing area aligned with the filter-receiving opening, and an adhesive bead on the image sensor IC surrounding the image sensing area. Furthermore, an infrared (IR) filter may be within the filter-receiving opening and have peripheral portions contacting the adhesive bead. | 01-29-2015 |
20150060891 | OPTOELECTRONICS ASSEMBLY AND METHOD OF MAKING OPTOELECTRONICS ASSEMBLY - An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly. | 03-05-2015 |