| Patent application number | Description | Published |
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| 20100140788 | MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump. | 06-10-2010 |
| 20100167471 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 07-01-2010 |
| 20100187651 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME - Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit. | 07-29-2010 |
| 20110156239 | METHOD FOR MANUFACTURING A FAN-OUT EMBEDDED PANEL LEVEL PACKAGE - A method for manufacturing a fan-out embedded panel-level package. Film having an adhesive on each side is applied to the non-active face of a plurality of semiconductor die while the die are still in wafer form. The die are singulated from the wafer and placed on a carrier, using the adhesive on the unused side of the film to attach the die to the carrier. Encapsulant material is dispensed onto the carrier adjacent to the die, providing an exposed surface on the encapsulant material approximately even with the active faces of the die. Elements of the redistribution layer such as conductors and fan-out pads are applied to this surface. A solder ball array is placed on the fan-out pads and then the die are re-singulated by cutting through the encapsulation material and the carrier, yielding individual electronic packages. | 06-30-2011 |
| 20120038043 | MANUFACTURING FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump. | 02-16-2012 |
| 20120098104 | SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT - Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches. | 04-26-2012 |
| 20120161319 | BALL GRID ARRAY METHOD AND STRUCTURE - A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing. | 06-28-2012 |
| 20120161332 | METHOD FOR PRODUCING VIAS IN FAN-OUT WAFERS USING DRY FILM AND CONDUCTIVE PASTE, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 μm or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures. | 06-28-2012 |
| 20120168938 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor wafer has integrated circuits formed thereon and a top passivation layer applied. The passivation layer is patterned and selectively etched to expose contact pads on each semiconductor die. The wafer is exposed to ionized gas causing the upper surface of passivation layer to roughen and to slightly roughen the upper surface of the contact pads. The wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer and a reconstituted wafer formed. Redistribution layers are formed to complete the semiconductor package having electrical contacts for establishing electrical connections external to the semiconductor package, after which the wafer is singulated to separate the dice. | 07-05-2012 |
| 20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
| 20120168943 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package. | 07-05-2012 |
| 20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
| 20120171875 | RECONSTITUTED WAFER WARPAGE ADJUSTMENT - A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures. | 07-05-2012 |
| 20120244664 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 09-27-2012 |
| 20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
| 20130062764 | SEMICONDUCTOR PACKAGE WITH IMPROVED PILLAR BUMP PROCESS AND STRUCTURE - A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars. | 03-14-2013 |
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| 20090055168 | Word Detection - Methods, systems, and apparatus, including computer program products, in which data from web documents are partitioned into a training corpus and a development corpus are provided. First word probabilities for words are determined for the training corpus, and second word probabilities for the words are determined for the development corpus. Uncertainty values based on the word probabilities for the training corpus and the development corpus are compared, and new words are identified based on the comparison. | 02-26-2009 |
| 20090055381 | Domain Dictionary Creation - Methods, systems, and apparatus, including computer program products, to identify topic words in a document corpus that includes topic documents related to a topic are disclosed. A reference topic word divergence value based on the document corpus and the topic document corpus is determined. A candidate topic word divergence value for a candidate topic word is determined based on the document corpus and the topic document corpus. The candidate topic word is determined to be a topic word if the candidate topic word divergence value is greater than the reference topic word divergence value. | 02-26-2009 |
| 20100005086 | RESOURCE LOCATOR SUGGESTIONS FROM INPUT CHARACTER SEQUENCE - Methods, systems, and apparatus, including computer program products, in which an input method editor receives Roman character inputs, identifies keywords for candidate sets of a non-Roman character, and identifies an associated resource location. Upon identifying an associated resource location, associating the resource location with the candidate set of non-Roman characters. | 01-07-2010 |
| 20110050993 | MOTION ESTIMATING METHOD AND IMAGE PROCESSING APPARATUS - Disclosed are a motion estimating method for an image and an image processing apparatus. A motion estimating method of an image, the method including: calculating a candidate motion vector by using one of a forward motion estimation and a backward motion estimation from a reference block extracted from one of first and second images that are input consecutively, and a search area extracted from the other one of the first and second images; calculating a pseudo motion vector corresponding to the other one of the forward motion estimation and the backward motion estimation by using the candidate motion vector; and interpolating the first and second images by using at least one of the candidate motion vector and the pseudo motion vector. | 03-03-2011 |
| 20110137642 | Word Detection - Methods, systems, and apparatus, including computer program products, in which data from web documents are partitioned into a training corpus and a development corpus are provided. First word probabilities for words are determined for the training corpus, and second word probabilities for the words are determined for the development corpus. Uncertainty values based on the word probabilities for the training corpus and the development corpus are compared, and new words are identified based on the comparison. | 06-09-2011 |
| 20110238413 | DOMAIN DICTIONARY CREATION - Methods, systems, and apparatus, including computer program products, to identify topic words in a collection of documents that includes topic documents related to a topic are disclosed. A reference topic word divergence value based on a document collection and the topic document collection is determined. A candidate topic word divergence value for a candidate topic word is determined based on the document collection and the topic document collection. The candidate topic word is determined to be a topic word if the candidate topic word divergence value is greater than the reference topic word divergence value. | 09-29-2011 |
| 20120173222 | METHOD AND SYSTEM FOR FACILITATING TEXT INPUT - A method and system for facilitating text input is disclosed. The method comprises: invoking an input assistant from within an application in an operating environment at a client, the input assistant being a standalone input service within the same operating environment as the application, receiving a text string from a user in an input field of the application, providing, by the input assistant, input prediction for completing the text string, selecting an input text of at least one word in the input field of the application, retrieving, by the input assistant, text content related to the input text from one or more text assistance services in communication with the input assistant, presenting the received text content to the user for assistance in the user's text input. | 07-05-2012 |
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| 20100240980 | Wan-Based Remote Mobile Monitoring Method And Device Of Electrophysiological Data - A WAN-based remote mobile monitoring method and device of electrophysiological data, including microprocessor circuit, electrophysiological signal sampling processing circuit, data storage circuit, image liquid crystal circuit, real-time clock, emergent calling circuit, working power supply management circuit, wireless network interface circuit, USB interface circuit, etc, has the in-built binding IP address of the remote electrophysiological data monitoring server, TCP/IP protocol, PPP protocol and BlueTooth protocol. Application controls self-adaptive analysis computing, exception event warning and alarming privilege graded setting, event data package combination, network digital communication, data storage circuit area management, safety information data storage management and remote emergent calling of the remote mobile monitoring devices. It can have access to Internet in motion and roaming access to Internet by inter-network switch, and have access to the exterior networks wirelessly including Internet, LAN, ADSL, VDSL, ISDN, etc, for digital communication with the remote electrophysiological data monitoring server. | 09-23-2010 |
