Yongduk
Yongduk Jin, Seoul KR
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20130160839 | SOLAR CELL - A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region which is positioned at a front surface of the substrate and has a second conductive type different from the first conductive type, a front passivation region including a plurality of layers which are sequentially positioned on the emitter region, a back passivation region which is positioned on a back surface opposite the front surface of the substrate and includes three layers, a plurality of front electrodes which pass through the front passivation region and are connected to the emitter region, and at least one back electrode which passes through the back passivation region and is connected to the substrate. | 06-27-2013 |
20130298974 | SOLAR CELL, METHOD FOR MANUFACTURING DOPANT LAYER, AND METHOD FOR MANUFACTURING SOLAR CELL - In a method of manufacturing a solar cell includes forming a dopant layer by doping a dopant of a first conductive type and a count dopant of a second conductive type opposite to the first conductive type to a surface of a semiconductor substrate. Here, a doping amount of the count dopant is less than a doping amount of the dopant. | 11-14-2013 |
20130298975 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell according to an embodiment includes a semiconductor substrate; a first dopant layer formed at one surface of the semiconductor substrate; and a first electrode electrically connected to the first dopant layer. At least a part of the first dopant layer includes a pre-amorphization element, and a concentration of the pre-amorphization element in one portion of the first dopant layer is different from a concentration of the pre-amorphization element in another portion of the first dopant layer. | 11-14-2013 |
20130344647 | METHOD FOR MANUFACTURING SOLAR CELL AND DOPANT LAYER THEREOF - A method for manufacturing a dopant layer of a solar cell according to an embodiment of the invention includes: ion-implanting a dopant to a substrate; and heat-treating for an activation of the dopant. In the heat-treating for the activation, the substrate is heat-treated at a first temperature after an anti-out-diffusion film is formed at a temperature lower than the first temperature under a first gas atmosphere. | 12-26-2013 |
Yongduk Kim, Daegu KR
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20130278158 | OLED LIGHTING MODULE - An OLED lighting apparatus includes: an OLED light panel; a first electrode; a second electrode; and at least one resistor connected between the OLED light panel and at least one of the first and second electrodes; first sets of terminals on opposite sides of the module connected to the first and second electrodes; and second sets of terminals on opposite sides of the module, wherein the lighting circuit is connected in series between the first sets of terminals. | 10-24-2013 |
Yongduk Lee, Seoul KR
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20120273959 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP - A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer. | 11-01-2012 |
20120273960 | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Encapsulant with TMV for Vertical Interconnect in POP - A semiconductor device has a carrier or first conductive layer with a plurality of TSV semiconductor die mounted over the carrier or first conductive layer. An encapsulant is deposited around the first semiconductor die and over the carrier or first conductive layer to embed the first semiconductor die. A conductive TMV is formed through the encapsulant. A second conductive layer is formed over a first surface of the encapsulant. A first insulating layer is formed over the first surface of the encapsulant while exposing portions of the second conductive layer. A second insulating layer is formed over the second surface of the encapsulant while exposing portions of the first conductive layer. Alternatively, a first interconnect structure is formed over the first surface of the encapsulant. The carrier is removed and a second interconnect structure is formed over a second surface of the encapsulant. | 11-01-2012 |
20120326325 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate. | 12-27-2012 |
Yongduk Lee, Paju-Si KR
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20140146058 | METHOD OF DETECTING DATA BIT DEPTH AND INTERFACE DEVICE FOR DISPLAY DEVICE USING THE SAME - A method of detecting a data bit depth and an interface device for a display device using the same are disclosed. The method includes confirming a physical connection between a transmitting terminal and a receiving terminal and then transmitting a clock data recovery (CDR) training pattern signal from the transmitting terminal to the receiving terminal, outputting clocks from a CDR circuit of the receiving terminal using the CDR training pattern signal, receiving an alignment training pattern signal subsequent to the CDR training pattern signal from the transmitting terminal to the receiving terminal, and counting bits of pixel data included in the alignment training pattern signal or the clocks and determining a data bit depth of input data based on a count result, in the interface receiving terminal. | 05-29-2014 |