Patent application number | Description | Published |
20080201895 | Robot cleaner system having robot cleaner and docking station - Disclosed is a robot cleaner system having superior functions of sucking dust and exhausting dust to a docking station. The robot cleaner includes a dust suction port to suck dust, a dust collecting chamber to collect dust introduced through the dust suction port, a dust exhaust port to exhaust dust collected in the dust collecting chamber to the docking station, a connection path extending from the dust suction port to the dust exhaust port in adjacent to the dust collecting chamber, and a valve device provided between the connection path and the dust collecting chamber, an opening/closing of the valve device allowing the dust collecting chamber to selectively communicate with the dust suction port or the dust exhaust port according to a pressure difference between the dust collecting chamber and the connection path. | 08-28-2008 |
20080235897 | Robot cleaner with improved dust collector - A robot cleaner having a configuration capable of improving an ability to collect dust, etc. is disclosed. The robot cleaner includes a suction hole to suction dust, a dust collector to receive the dust suctioned through the suction hole, and a rotating brush provided at a side of the suction hole. The robot cleaner is configured to sweep up and collect the dust into the dust collector by a drive force of the rotating brush. | 10-02-2008 |
20080249661 | Wall-following robot cleaner and method to control the same - A robot cleaner that cleans a cleaning region while traveling the cleaning region and a method to control the same are provided. The robot cleaner can uniformly clean a cleaning region based on a wall-following technique which allows the robot cleaner to travel along the outline of the cleaning region. The method selects, as a reference wall, a wall at a left or right side of the robot cleaner at a start position of the robot cleaner based on a left or right-based travel algorithm, which allows the robot cleaner to travel along a left or right wall, and controls the robot cleaner to travel the cleaning region in a zigzag travel pattern in which the robot cleaner moves a predetermined distance in a direction perpendicular to the reference wall at specific intervals along the selected reference wall while following the selected reference wall. | 10-09-2008 |
20080268592 | Flash memory device and method of fabricating the same - Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer. | 10-30-2008 |
20080283873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via. | 11-20-2008 |
20080318406 | SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level. | 12-25-2008 |
20090121277 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 05-14-2009 |
20090141562 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 06-04-2009 |
20090278192 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern. | 11-12-2009 |
20100001328 | SEMICONDUCTOR DEVICE HAVING AN ANTI-PAD PEELING-OFF STRUCTURE - A bonding pad having an anti-pad peeling-off structure is disclosed. In a method of forming the bonding pad, after a metal pad layer is formed, a slit is formed in the metal pad layer. A protecting layer is formed on the metal pad layer. The protecting layer is partially removed to expose the metal pad such that a portion of the protecting layer remains in the slits to be connected to the main protecting layer. The protecting layer formed in the slit is connected to the protecting layer such that the residual protecting layer pattern buffer when physical impacts are generated, to prevent peeling-off of the metal pad layer. | 01-07-2010 |
20100103744 | Non-volatile memory device and method of driving the same - A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors. | 04-29-2010 |
20100289071 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 11-18-2010 |
20110175175 | SEMICONDUCTOR DEVICE FOR APPLYING COMMON SOURCE LINES WITH INDIVIDUAL BIAS VOLTAGES - Provided is a semiconductor device for applying common source lines with individual bias voltages. The device includes a substrate, cell transistors arrayed in a cell matrix shape on the substrate and configured to have gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions. Word lines are configured to electrically interconnect the gate electrodes with each other. Common source lines are shared between only a pair of the neighboring word lines and are configured to electrically interconnect the common source regions with each other. Drain metal contacts and source metal contacts are arranged in a straight line on the drain regions. Bit lines are electrically connected to the drain metal contacts. And impurity regions are configured to control the threshold voltage of the channel regions. | 07-21-2011 |
20110182117 | METHOD OF PROGRAMMING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string. | 07-28-2011 |
20110277269 | Robot cleaner with improved dust collector - A robot cleaner including a suction hole to suction dust, a blower to generate a suction force to suction the dust, a dust collector to receive the dust suctioned by said suction force through the suction hole, and a rotating brush to sweep up and collect the dust into the dust collector through the suction hole by a drive force of the rotating brush. The dust collector includes a backflow preventing member movable between an open position and a closed position. The backflow preventing member is pivotably rotatable in an air suction direction by the suction force of the blower to the open position and is adapted to return to the closed position to prevent the dust in the dust collector from being discharged through the suction hole upon stoppage of the blower. | 11-17-2011 |
20110316092 | Mask Rom - A mask read-only memory (ROM) includes parallel doping lines of a second conductivity type formed in a substrate of a first conductivity type, a first insulation film formed on the doping lines and the substrate, conductive pads fainted on the first insulation film, a second insulation film formed on the first insulation film and the conductive pads, parallel wires formed on the second insulation film extending perpendicular to the doping lines, contact plugs formed in the first insulation film that connect the doping lines to the conductive pads, and vias formed in the second insulation film that connect the conductive pads to the wires, wherein crossings of the doping lines and the wires define memory cells, contact plugs and vias are formed in memory cells of a first type, and at least one of the contact plug and via are missing from memory cells of a second type. | 12-29-2011 |
20120018797 | NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING AND DRIVING THE SAME - A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region. | 01-26-2012 |
20120068249 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 03-22-2012 |
20120070949 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region. | 03-22-2012 |
20130227812 | ROBOT CLEANER WITH IMPROVED DUST COLLECTOR - A robot cleaner including a suction hole to suction dust, a blower to generate a suction force to suction the dust, a dust collector to receive the dust suctioned by said suction force through the suction hole, and a rotating brush to sweep up and collect the dust into the dust collector through the suction hole by a drive force of the rotating brush. The dust collector includes a backflow preventing member movable between an open position and a closed position. The backflow preventing member is pivotably rotatable in an air suction direction by the suction force of the blower to the open position and is adapted to return to the closed position to prevent the dust in the dust collector from being discharged through the suction hole upon stoppage of the blower. | 09-05-2013 |
20140264538 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate. | 09-18-2014 |