Yong Keon
Yong Keon Choi, Bucheon-City KR
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20090174004 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions. | 07-09-2009 |
Yong Keon Choi, Gyeonggi-Do KR
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20090072299 | SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE MOS TRANSISTOR AND FABRICATION METHOD THEREOF - A semiconductor device having a high voltage MOS transistor. The device includes a gate oxide layer disposed between a gate electrode and a substrate on an active area and having relatively thick portions at edges thereof. A fabrication method includes forming on the substrate is a nitride layer having an opening in a high voltage region. An oxide layer is deposited over the substrate and anisotropically etched to remain only on sidewalls of the opening. A first gate oxide layer is formed on the substrate in the opening, and the nitride layer is removed. Then a second gate oxide layer is formed over the substrate such that the second gate oxide layer has a relatively thinner thickness than the first gate oxide layer. Gate electrodes are then formed in the high voltage region and the low voltage region. | 03-19-2009 |
Yong Keon Choi, Seoul KR
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20130092995 | ELECTRICAL ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND MANUFACTURING METHOD THEREOF - An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced. | 04-18-2013 |