Patent application number | Description | Published |
20090193313 | Method and apparatus for decoding concatenated code - Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders. | 07-30-2009 |
20090241008 | Memory devices and encoding and/or decoding methods - Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword. | 09-24-2009 |
20090241009 | Encoding and/or decoding memory devices and methods thereof - Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device. | 09-24-2009 |
20090276687 | METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA - A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P. | 11-05-2009 |
20090282319 | HIERARCHICAL DECODING APPARATUS - A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination. | 11-12-2009 |
20090285023 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include a multi-bit cell array including a plurality of multi-bit cells, a programming unit configured to program a first data page in the plurality of multi-bit cells and to program a second data page in the multi-bit cells with the programmed first data page, a first controller configured to divide the multi-bit cells with the programmed first data page into a first group and a second group, and a second controller configured to set a target threshold voltage interval of each of the multi-bit cells included in the first group based on first read voltage levels and the second data page, and to set a target threshold voltage interval of each of the multi-bit cells included in the second group based on second read threshold voltage levels and the second data page. | 11-19-2009 |
20090287975 | Memory device and method of managing memory data error - Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device. | 11-19-2009 |
20090296466 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-bit cell array that includes a plurality of memory cells; a controller that extracts state information of each of the memory cells, divides the plurality of memory cells into a first group and a second group, assigns a first verify voltage to memory cells of the first group and assigns a second verify voltage to memory cells of the second group; and a programming unit that changes a threshold voltage of each memory cell of the first group until the threshold voltage of each memory cell of the first group is greater than or equal to the first verify voltage, and changes a threshold voltage of each memory cell of the second group until the threshold voltage of each memory cell of the second group is greater than or equal to the second verify voltage. | 12-03-2009 |
20090296486 | Memory device and memory programming method - Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell. | 12-03-2009 |
20090307566 | ITERATIVE DECODING METHOD AND APPARATUS - An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N. | 12-10-2009 |
20100002506 | Memory device and memory programming method - Provided are memory devices and memory programming methods. A memory device may include: a multi-level cell array that includes a plurality of multi-level cells; a programming unit that programs a first data page in the plurality of multi-level cells and programs a second data page in a multi-level cell from among the plurality of multi-level cells in which the first data page is programmed; an error analysis unit that analyzes read error information corresponding to the first data page based on a read voltage level to determine whether to correct a read error based on the analyzed read error information; and a controller that adjusts the read voltage level of the first data page depending on the determination result. Through this, it is possible to reduce an error occurrence when reading and/or programming a data page. | 01-07-2010 |
20100020620 | Memory device and method of programming thereof - Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells. | 01-28-2010 |
20100027335 | Memory device and wear leveling method - The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells. | 02-04-2010 |
20100077279 | Non-Volatile Memory Devices, Systems, and Data Processing Methods Thereof - Provided are data processing methods for a non-volatile memory. The data processing methods include obtaining read data and erasure information from the non-volatile memory and correcting an error in the read data by referencing the erasure information obtained from the non-volatile memory. Memory systems may be provided. Such memory systems may include a non-volatile memory and a memory controller that is operable to perform an error correction operation according to the methods described herein. | 03-25-2010 |
20100088574 | DATA STORAGE SYSTEM AND DEVICE WITH RANDOMIZER/DE-RANDOMIZER - A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data. | 04-08-2010 |
20100091578 | Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same - Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased. | 04-15-2010 |
20100115225 | Memory Device and Memory System Including the Same - Provided is a memory device. The memory device includes a word line and a plurality of memory cells connected to the word line. The plurality of memory cells forms a page, and the number of sectors configuring the page and the size of each of the sectors can be changed. | 05-06-2010 |
20100115377 | METHOD OF ESTIMATING AND CORRECTING ERRORS IN MEMORY CELLS - A method, implemented by at least an error correction code (ECC) decoder and a controller, estimates and corrects errors in memory cells. The method includes identifying a first candidate group of memory cells having an error-generation possibility using a first method for error estimation; identifying a second candidate group of memory cells having an error-generation possibility using a second method for error estimation; and correcting errors in at least one cell commonly included in the first and second candidate groups. | 05-06-2010 |
20100118608 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM, AND METHOD DETERMINING READ VOLTAGE IN SAME - A non-volatile semiconductor memory device and related method of determining a read voltage are disclosed. The non-volatile semiconductor memory device includes; a memory cell array including a plurality of memory cells, a read voltage determination unit configured to determine an optimal read voltage by comparing reference data obtained during a program operation with comparative data obtained during a subsequent read operation and changing a current read voltage to a new read voltage based on a result of the comparison, and a read voltage generation unit configured to generate the new read voltage in response to a read voltage control signal provided by the read voltage determination unit. | 05-13-2010 |
20100174959 | DECODING METHOD AND MEMORY SYSTEM DEVICE USING THE SAME - A decoding method includes performing a first decoding method and performing a second decoding method when decoding of the first decoding method fails. The first decoding method includes updating multiple variable nodes and multiple check nodes using probability values of received data. The second decoding method includes selecting at least one variable node from among the multiple variable nodes; correcting probability values of data received in the selected at least one variable node; updating the variable nodes and the check nodes using the corrected probability values; and determining whether decoding of the second decoding method is successful. | 07-08-2010 |
20100174966 | DEVICE AND METHOD PROVIDING 1-BIT ERROR CORRECTION - A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected. | 07-08-2010 |
20100202198 | Semiconductor memory device and data processing method thereof - Provided is a data processing method in a semiconductor memory device. The data processing method arranges data, which is to be programmed in a row and column of a nonvolatile memory device, in a row or column direction. The data processing method encodes the programmed data into a modulation code in the row or column direction such that adjacent pairs of memory cells of the nonvolatile memory device are prevented from being programmed into first and second states. | 08-12-2010 |
20100235711 | Data Processing System with Concatenated Encoding and Decoding Structure - A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword. | 09-16-2010 |
20100238705 | NONVOLATILE MEMORY DEVICE AND METHOD SYSTEM INCLUDING THE SAME - A nonvolatile memory device performs interleaving of data to be stored in each wordline (memory page), or of data to be stored in multiple wordlines (memory pages). The NVM includes a memory cell array, a storage circuit of a de-interleaving circuit, and a read/write circuit. The storage circuit of the de-interleaving circuit is configured to store program data to be written interleaved into the memory cell array. The read/write circuit is configured to control the interleaved/deinterleaved data input/output between the memory cell array and the storage circuit. The write operation unit size may be the same or different from the read operation unit size. The storage circuit stores the program data of integer k times of a common divisor of a read operation unit size and a write operation unit size of the read/write circuit, wherein k may equal ‘m’ (the number of bits stored in each memory cell of the NVM). | 09-23-2010 |
20100241928 | Data Processing System Having ECC Encoding and Decoding Circuits Therein with Code Rate Selection Based on Bit Error Rate Detection - A data processing system includes an error checking and correction (ECC) encoding circuit, an integrated circuit memory and a code rate control circuit. The ECC encoding circuit is configured to selectively apply a plurality of unique ECC code rates to write data received by the data processing system during an operation to convert the write data into encoded data, in response to a code rate selection signal. The integrated circuit memory includes a plurality of storage regions therein. These storage regions are configured to receive respective portions of the encoded data from the ECC encoding circuit. The code rate control circuit is configured to generate the code rate selection signal. This code rate selection signal has a value that specifies the corresponding ECC code rate to be applied to respective portions of the write data. | 09-23-2010 |
20100246286 | Nonvolatile memory device, method, system including the same, and operating method thereof - In a method of operating a nonvolatile memory device, data is read using a read level, and a range of logic values for erasure-decoding the read data is set. The bits of the read data corresponding to the set range of logic values are set as erasure bits, and an erasure decoding operation is performed. | 09-30-2010 |
20100248634 | METHOD OF CYCLIC DELAY DIVERSITY WITH THE OPTIMAL CYCLIC DELAY VALUE, AND TRANSMITTER PERFORMING THE SAME - Disclosed are an apparatus and method of determining an optimal cyclic delay value. The method of determining the optimal cyclic delay value includes determining a Signal-to-Interference and Noise Ratio (SINR) function depending on a diversity order; determining a channel estimation error variance function; and determining an SINR being required for a system according to the SINR function and the channel estimation error variance function. | 09-30-2010 |
20100251077 | STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME - A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory. | 09-30-2010 |
20100287447 | MEMORY SYSTEM IDENTIFYING AND CORRECTING ERASURE USING REPEATED APPLICATION OF READ OPERATION - Provided is a read method for a memory system. The read method determines whether a read data error is correctable. The read method applies a plurality of read operations at a set read voltage level to identify erasure candidates, when the error is uncorrectable. The read method performs erasure decoding using an error correction code or an error detection code for the erasure candidates. | 11-11-2010 |
20100296350 | METHOD OF SETTING READ VOLTAGE MINIMIZING READ DATA ERRORS - A method setting a read voltage to minimize data read errors in a semiconductor memory device including multi-bit memory cells. In the method, a read voltage associated with a minimal number of read data error is set based on a statistic value of a voltage distribution corresponding to each one of a plurality of voltage states. | 11-25-2010 |
20100302850 | Storage device and method for reading the same - The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution. | 12-02-2010 |
20100306583 | Memory Systems and Defective Block Management Methods Related Thereto - Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition. | 12-02-2010 |
20110032759 | MEMORY SYSTEM AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises counting a number of state pairs in a unit of input data, modulating the unit of input data to reduce the number of state pairs contained therein, and programming the modulated unit of input data in the nonvolatile memory device. Each state pair comprises data with a first state and designated for programming in a memory cell connected to a first word line, and data with a second state and designated for programming in a memory cell connected to a second word line adjacent to the first word line. The memory cell connected to the first word line is adjacent to the memory cell connected to the second word line. | 02-10-2011 |
20110038207 | FLASH MEMORY DEVICE, PROGRAMMING AND READING METHODS PERFORMED IN THE SAME - The flash memory device includes a control logic circuit and a bit level conversion logic circuit. The control logic circuit programs first through N | 02-17-2011 |
20110040929 | METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE - A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence. | 02-17-2011 |
20110125975 | INTERLEAVING APPARATUSES AND MEMORY CONTROLLERS HAVING THE SAME - An interleaving apparatus may include a first buffer unit configured to buffer input data in units having a size of a sector to generate sector unit data, an encoding unit configured to encode the sector unit data and generate a plurality of parity codes based on the encoding, a second buffer unit configured to interleave the sector unit data and the parity codes and generate interleaving data based on the interleaving, the second buffer unit including a plurality of output buffers configured to store the interleaving data, and an output unit configured to output the interleaving data. | 05-26-2011 |
20110209031 | Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices - Methods of operating nonvolatile memory devices include testing a plurality of strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other ones of the plurality of strings. An identity of the at least one weak string may be stored as weak column information. This weak column information may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on a first plurality of bits of data read from the plurality of strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the first plurality of bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the first plurality of data bits. | 08-25-2011 |
20110216588 | MULTI-BIT CELL MEMORY DEVICES USING ERROR CORRECTION CODING AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of multi-bit memory cells. A plurality of input data bits are encoded according to an error correction code to generate a codeword including a plurality of groups of bits. Respective ones of the plurality of multi-bit memory cells are programmed to represent respective ones of the groups of bits of the codeword. The groups of bits of the codeword may be groups of consecutive bits. In some embodiments, the multi-bit memory cells are each configured to store in bits and a length of the codeword is an integer multiple of m. Data may be read from the multi-bit memory cells in page units or cell units to recover the codeword, and the recovered code word may be decode according to the error correction code to recover the input data bits. | 09-08-2011 |
20110216590 | NONVOLATILE MEMORY DEVICE USING INTERLEAVING TECHNOLOGY AND PROGRAMMMING METHOD THEREOF - A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2 | 09-08-2011 |
20110216598 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 09-08-2011 |
20110219288 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING CONTROLLER, AND METHOD OF OPERATING MEMORY SYSTEM INCLUDING THE SAME - An method of operating a memory system including a nonvolatile memory device and a controller. The method includes receiving a source word, converting the received source word to a codeword, and programming the converted codeword in the nonvolatile memory device. A length of the converted codeword can be greater than a length of the received source word, and a difference between the numbers of first and second digital bits of the converted codeword can be less than a reference value. | 09-08-2011 |
20110246853 | SEMICONDUCTOR DEVICE AND DECODING METHOD THEREOF - An error control coding (ECC) circuit includes a first decoder, a second decoder, and a controller. The first decoder receives encoded data comprising a first parity and a second parity. The first decoder decodes the encoded data to a first code by using the first parity. The second decoder is connected to the first decoder. The second decoder is configured to decode the encoded data when the first decoder is deactivated and decode the first code using the second parity when the first decoder is deactivated. The controller transmits a control signal to the first decoder and the second decoder to control the first decoder and the second decoder. | 10-06-2011 |
20110276857 | DATA STORAGE DEVICE AND PROGRAM METHOD THEREOF - A data storage device includes a non-volatile memory device including a plurality of memory cells and a memory controller. The memory controller is configured to modify an arrangement of program data and to program the modified program data into the plurality of memory cells. The memory controller modifies the program data to eliminate a given data pattern causing physical interference between adjacent memory cells from the modified program data. | 11-10-2011 |
20110283166 | STORAGE DEVICE HAVING A NON-VOLATILE MEMORY DEVICE AND COPY-BACK METHOD THEREOF - A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation. | 11-17-2011 |
20120020156 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES PERFORMING THE METHOD - A method of programming multi-level cells included in a spare region, the method including programming first page data and at least one first dummy data in a first multi-level cell; and programming second page data and at least one second dummy data in a second multi-level cell. | 01-26-2012 |
20120069657 | MEMORY DEVICE AND SELF INTERLEAVING METHOD THEREOF - A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array. | 03-22-2012 |
20120166708 | FLASH MEMORY DEVICES, DATA RANDOMIZING METHODS OF THE SAME, MEMORY SYSTEMS INCLUDING THE SAME - Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer. | 06-28-2012 |
20120215963 | Semiconductor Memory Systems that Include Data Randomizers and Related Devices, Controllers and Methods - A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period. | 08-23-2012 |
20120221775 | NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF - An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded. | 08-30-2012 |
20120233518 | Data Processing Systems And Methods Providing Error Correction - A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed. | 09-13-2012 |
20120290783 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device including a randomizer and a memory system including the memory device are provided. The memory device includes: a randomizer including a sequence generator which generates a first sequence from a seed and a converter which converts the first sequence into a second sequence in response to a conversion factor, the randomizer randomizing data to be programmed using the second sequence and outputting the randomized data; and a storage area which receives the randomized data from the randomizer and storing the randomized data. | 11-15-2012 |
20130018934 | METHODS FOR OPERATING CONTROLLERSAANM Kim; Yong JuneAACI SeoulAACO KRAAGP Kim; Yong June Seoul KRAANM Chung; Jung SooAACI SeoulAACO KRAAGP Chung; Jung Soo Seoul KRAANM Kong; Jun JinAACI Yongin-siAACO KRAAGP Kong; Jun Jin Yongin-si KRAANM Son; HongrakAACI Anyang-siAACO KRAAGP Son; Hongrak Anyang-si KR - A method for operating a controller may include storing a pseudo noise (PN) sequence provided from a PN sequence generator in an i-th area of a seed table and cyclically shifting the PN sequence from the i-th area to an (i+1)-th area in the table to form the table. The table may include row and column areas. A method for operating a controller may include receiving a sequence from a sequence generator, splitting the sequence into seed units, storing split sequences in a j-th area of the seed table, and forming the table including the seed units corresponding to the split sequences stored in the j-th area. A method for operating a controller may include storing a sequence provided from a sequence generator in a seed table that includes a plurality of areas and cyclically shifting the sequence in the table until a seed is formed in each area. | 01-17-2013 |
20130031443 | METHOD OF OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM, MEMORY CARD AND PORTABLE ELECTRONIC DEVICE INCLUDING THE MEMORY CONTROLLER - A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages. | 01-31-2013 |
20140056064 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 02-27-2014 |
20140082458 | Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices - Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on bits of data read from the strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the data bits. | 03-20-2014 |
20140185375 | MEMORY SYSTEM TO DETERMINE INFERENCE OF A MEMORY CELL BY ADJACENT MEMORY CELLS, AND OPERATING METHOD THEREOF - Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols. | 07-03-2014 |