Patent application number | Description | Published |
20100225637 | DISPLAY DRIVING SYSTEM WITH MONITORING UNIT FOR DATA DRIVER - A display driving system includes a timing controller configured to receive a data signal composed of image data and generate a control signal such as a clock signal; an interface configured to transmit the data signal and the control signal to a plurality of data drivers; the data drivers configured to receive the data signal and the control signal through the interface and supply received signals to a display panel to display an image; and a monitoring unit configured to feed back LOCK signals indicative of state information of the data drivers to the timing controller such that the data drivers can be monitored. | 09-09-2010 |
20110181558 | DISPLAY DRIVING SYSTEM USING TRANSMISSION OF SINGLE-LEVEL SIGNAL EMBEDDED WITH CLOCK SIGNAL - A display driving system includes a timing control section having an LVDS receiving unit for receiving data signals, a data processing unit for temporarily storing the data signals, processing the data signals and outputting processed data signals, a timing generation unit for generating clock signals and timing control signals, and a transmission unit for transmitting the data signals; and a panel driving section having row driving units for sequentially emitting gate signals toward a display panel and column driving units for receiving the signals transmitted through signal lines from the transmission unit and supplying the received signals to the display panel. In the timing control section, the transmission unit has driving parts which embed the clock signals between the data signals at the same level and generate and output single level transmission data. | 07-28-2011 |
20110242066 | DISPLAY DRIVING SYSTEM USING SINGLE LEVEL DATA TRANSMISSION WITH EMBEDDED CLOCK SIGNAL - A display driving system using single level data transmission with embedded clock signals. The display driving system is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words. | 10-06-2011 |
20110286562 | RECEIVER HAVING CLOCK RECOVERY UNIT BASED ON DELAY LOCKED LOOP - A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal. | 11-24-2011 |
20120194224 | PRE-EMPHASIS CIRCUIT AND DIFFERENTIAL CURRENT SIGNALING SYSTEM HAVING THE SAME - Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver. | 08-02-2012 |
20120306551 | CIRCUIT AND METHOD FOR PREVENTING FALSE LOCK AND DELAY LOCKED LOOP USING THE SAME - The present invention relates to a false lock prevention circuit and method which is used to cause a delayed locked loop (DLL) to escape from false lock such as harmonic lock or stuck lock, when the false lock occurred in the DLL, and a DLL using the same. The false lock prevention circuit includes a harmonic lock detector configured to detect harmonic lock and a stuck lock detector configured to detect stuck lock. The harmonic lock detector includes a plurality of flip-flops configured to sample a plurality of delayed clocks and a logic unit. The harmonic lock detector compares a reference clock signal with the plurality of delayed clock signals, and detects whether or not the positive edges deviate from one cycle of the reference clock signal. | 12-06-2012 |
20130278591 | EMBEDDED DISPLAYPORT SYSTEM AND METHOD FOR CONTROLLING PANEL SELF REFRESH MODE - Provided are an embedded DisplayPort (eDP) system and a method for controlling a panel self refresh mode. The eDP system enters a panel self refresh (PSR) mode when an image to display is static in a general mode, and a sink device recovers a stream clock for displaying a static image in the PSR mode. | 10-24-2013 |
20140184291 | CIRCUIT FOR CONTROLLING VARIATION IN FREQUENCY OF CLOCK SIGNAL - Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked. | 07-03-2014 |