Patent application number | Description | Published |
20100013066 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip. | 01-21-2010 |
20110008048 | Optical system using optical signal and solid state drive module using the optical signal - An optical system and an SSD module that maintain optimal SI, PI and EMI characteristics without a shield based on a ground voltage and an impedance match. The optical system includes a solid state drive (SSD) module and an input/output (I/O) interface. The SSD module includes a plurality of solid state memory units. The input/output (I/O) interface receives data to be written to at least one of the solid state memory units from a main memory unit, the input/output (I/O) interface transmits data written in at least one of the solid state memory units to the main memory unit. The SSD module and the I/O interface transmit and receive data using an optical medium. | 01-13-2011 |
20110241168 | PACKAGE ON PACKAGE STRUCTURE - A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate. | 10-06-2011 |
20110304015 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI). | 12-15-2011 |
20110304763 | IMAGE SENSOR CHIP AND CAMERA MODULE HAVING THE SAME - An image sensor chip, a camera module, and devices incorporating the image sensor chip and camera module include a light receiving unit on which light is incident, a logic unit provided to surround the light receiving unit, and an electromagnetic wave shielding layer formed on the logic unit and not formed on the light receiving unit. | 12-15-2011 |
20110316119 | SEMICONDUCTOR PACKAGE HAVING DE-COUPLING CAPACITOR - Provided is a semiconductor package including a de-coupling capacitor. The semiconductor package includes a substrate, on an upper surface of which a semiconductor chip is mounted; a plurality of first conductive bumps that are disposed on a lower surface of the substrate and that electrically connect the substrate to an external device; and a de-coupling capacitor that is disposed on the lower surface of the substrate and includes an electrode portion and at least one dielectric layer, wherein the electrode portion of the de-coupling capacitor includes second conductive bumps that electrically connect the substrate to an external device. | 12-29-2011 |
20110317381 | EMBEDDED CHIP-ON-CHIP PACKAGE AND PACKAGE-ON-PACKAGE COMPRISING SAME - An embedded chip-on-chip package comprises a printed circuit board having a recessed semiconductor chip mounting unit, a first semiconductor chip embedded in the recessed semiconductor chip mounting unit, and a second semiconductor chip mounted on the first semiconductor chip and the printed circuit board. | 12-29-2011 |
20120064827 | SEMICONDUCTOR DEVICE INCLUDING COUPLING CONDUCTIVE PATTERN - A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern. | 03-15-2012 |
20120080222 | CIRCUIT BOARD INCLUDING EMBEDDED DECOUPLING CAPACITOR AND SEMICONDUCTOR PACKAGE THEREOF - A circuit board including an embedded decoupling capacitor and a semiconductor package thereof are provided. The circuit board may include a core layer including an embedded decoupling capacitor, a first build-up layer at one side of the core layer, and a second build-up layer at the other side of the core layer, wherein the embedded decoupling capacitor includes a first electrode and a second electrode, the first build-up layer includes a first via contacting the first electrode, and the second build-up layer includes a second via contacting the first electrode. | 04-05-2012 |
20120086109 | Semiconductor Device Including Shielding Layer And Fabrication Method Thereof - Example embodiments relate to a semiconductor device. The semiconductor device may include a first semiconductor chip including a semiconductor substrate, a first through via that penetrates the semiconductor substrate, a second semiconductor chip stacked on one plane of the first semiconductor chip, and a shielding layer covering at least one portion of the first and/or second semiconductor chip and electrically connected to the first through via. | 04-12-2012 |
20120126431 | SEMICONDUCTOR PACKAGE - A semiconductor package having improved EMI and crosstalk characteristics is provided. The semiconductor package includes a semiconductor package including a substrate, at least one first semiconductor chip formed on a top surface of the substrate and electrically connected to the substrate, and at least one second semiconductor chip formed on a top surface of the first semiconductor chip and electrically connected to the first semiconductor chip, wherein first and second conductive layers are formed on the top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the first conductive layer and the second conductive layer are connected to a ground portion. | 05-24-2012 |
20120139090 | STACKED PACKAGE STRUCTURE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package. | 06-07-2012 |
20120306062 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - A semiconductor device, a semiconductor package, and an electronic device are provided. The electronic device includes a first semiconductor package disposed on a circuit substrate. A second semiconductor package is provided on the circuit substrate and spaced apart from the first semiconductor package. An insulating electromagnetic shielding structure is provided on the top and the lateral surfaces of the first semiconductor package. A conductive electromagnetic shielding structure is provided on the circuit substrate to cover the first and second semiconductor packages and the insulating electromagnetic shielding structure. | 12-06-2012 |
20130043584 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 02-21-2013 |
20130163696 | APPARATUS FOR COMPENSATING FOR DISTORTION OF TRANSMITTER ARRAY IN RADIO COMMUNICATION SYSTEM AND METHOD FOR CONTROLLING THE SAME - Provided is a method in which a Digital Pre-Distorter (DPD) performs digital pre-distortion on a received In-phase (I) signal, a received Quadrature-phase (Q) signal, a feedback I signal, and a feedback Q signal; a mixer mixes a signal output from the DPD with a frequency signal output from an oscillator; each of n phase shifters phase-shifts a signal output from the mixer according to a preset beamforming pattern; each of n Power Amplifiers (PAs) amplifies a signal output from an associated phase shifter according to a gain, the PAs connected to the associated phase shifter on a one-to-one basis; each of n envelope detectors detects an envelope signal from a signal output from an associated PA, the envelope detector connected to the associated PA on a one-to-one basis; and a control unit determines whether the n PAs operate normally, using the envelope signals output from the n envelope detectors. | 06-27-2013 |
20130165059 | BEAMFORMING APPARATUS AND METHOD IN MOBILE COMMUNICATION SYSTEM - Provided is a beamforming apparatus in a receiver in a mobile communication system. The beamforming apparatus includes a Local Oscillator (LO) signal generator for generating an LO signal; a phase shifter for generating a predetermined number of phase-shifted LO signals with respect to the generated LO signal; a switching network for mapping the phase-shifted LO signals to RF signals received via a plurality of receive paths; and a mixer for mixing the RF signals with the mapped LO signals to down-convert a frequency of the RF signals. | 06-27-2013 |
20130168871 | SEMICONDUCTOR PACKAGE WITH PACKAGE ON PACKAGE STRUCTURE - A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated. | 07-04-2013 |
20130200509 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part. | 08-08-2013 |
20140110831 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a package substrate, an interposer chip, a first semiconductor chip, a thermal dissipation structure and a second semiconductor chip. The interposer chip may be mounted on the package substrate. The first semiconductor chip may be mounted on the interposer chip. The first semiconductor chip may have a size smaller than that of the interposer chip. The thermal dissipation structure may be arranged on the interposer chip to surround the first semiconductor chip. The thermal dissipation structure may transfer heat in the first semiconductor chip to the interposer chip. The second semiconductor chip may be mounted on the first semiconductor chip. Thus, the heat in the first semiconductor chip may be effectively transferred to the interposer chip through the thermal dissipation line. | 04-24-2014 |
20140151859 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate in which a plurality of wires are formed; at least one semiconductor chip electrically connected to portions of the plurality of wires; and a shielding can mounted on the substrate, surrounding the at least one semiconductor chip, electrically connected to at least one wire of the plurality of wires and including a soft magnetic material. The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI). | 06-05-2014 |
20140175679 | SEMICONDUCTOR DEVICES, PACKAGE SUBSTRATES, SEMICONDUCTOR PACKAGES, PACKAGE STACK STRUCTURES, AND ELECTRONIC SYSTEMS HAVING FUNCTIONALLY ASYMMETRIC CONDUCTIVE ELEMENTS - A package stack structure may an upper package include an upper package substrate having a first edge and a second edge opposite to the first edge. The upper package substrate has a first region arranged near the first edge and a second region arranged near the second edge. A first upper semiconductor device is mounted on the upper package substrate. The package stack structure may also include a lower package having a lower package substrate and a lower semiconductor device. The lower package is connected to the upper package through a plurality of inter-package connectors. The plurality of the inter-package connectors may include first inter-package connectors configured to transmit data signals; second inter-package connectors configured to transmit address/control signals; third inter-package connectors configured to provide a supply voltage for an address/control circuit; and fourth inter-package connectors configured to provide a supply voltage for a data circuit. | 06-26-2014 |
20140319701 | SEMICONDUCTOR CHIP AND A SEMICONDUCTOR PACKAGE HAVING A PACKAGE ON PACKAGE (POP) STRUCTURE INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate. | 10-30-2014 |
20140328023 | SEMICONDUCTOR PACKAGE HAVING EMI SHIELDING FUNCTION AND HEAT DISSIPATION FUNCTION - A semiconductor package includes a substrate, a semiconductor chip located on a top surface of the substrate, signal lines formed on the top surface of the substrate and configured to allow different types of signals to input/output thereto/therefrom, a ground line unit formed on the top surface of the substrate and configured to divide the signal lines into signal lines to/from which the same types of signals are input/output to be isolated from one another, barrier walls configured to contact the ground line unit, and a heat dissipation unit disposed on the semiconductor chip, wherein the ground line unit includes diagonal ground lines located in diagonal directions of the substrate about the semiconductor chip, and the heat dissipation unit includes a thermal interface material (TIM) located on a top surface of the semiconductor chip, and a heat dissipation plate configured to cover the TIM and the substrate. | 11-06-2014 |
20140339692 | SEMICONDUCTOR PACKAGE STACK HAVING A HEAT SLUG - A semiconductor package stack, comprising: a lower semiconductor package including a lower semiconductor chip mounted on a lower package board; an upper semiconductor package stacked on the lower semiconductor package and including an upper semiconductor chip mounted on an upper package board, wherein the upper package board includes an opening configured to expose a lower surface of the upper semiconductor chip; and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of the lower semiconductor chip. | 11-20-2014 |
20150024545 | STACKED PACKAGE STRUCTURE AND METHOD OF MANUFACTURING A PACKAGE-ON-PACKAGE DEVICE - A stacked package structure is provided. The stacked package structure includes a stacked package including a lower semiconductor package, an upper semiconductor package disposed on the lower semiconductor package and spaced a predetermined distance apart from the lower semiconductor package, an inter-package connecting portion electrically connecting the lower semiconductor package and the upper semiconductor package while supporting a space therebetween, and an insulation layer disposed at least outside the inter-package connecting portion and filling the space between the lower semiconductor package and the upper semiconductor package, and an electromagnetic shielding layer surrounding lateral and top surfaces of the stacked package. | 01-22-2015 |