Yohn
Andrew Yohn, Swanzey, NH US
Patent application number | Description | Published |
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20110267416 | Laser Marking Using Scalable Fonts - A system directs a laser beam to mark a material with an alphanumeric code. Character and quality information corresponding to a mark to apply to the material with the laser beam can be received, a font definition that specifies character segments can be obtained, a set of multiple spaced locations can be generated from the character segments in accordance with the character and quality information, and the material can be marked with the laser beam by directing the laser beam to dwell at the locations and move between the locations without deactivating the laser beam. | 11-03-2011 |
20130300814 | Laser Marking Using Scalable Fonts - A system directs a laser beam to mark a material with an alphanumeric code. Character and quality information corresponding to a mark to apply to the material with the laser beam can be received, a font definition that specifies character segments can be obtained, a set of multiple spaced locations can be generated from the character segments in accordance with the character and quality information, and the material can be marked with the laser beam by directing the laser beam to dwell at the locations and move between the locations without deactivating the laser beam. | 11-14-2013 |
Brent D. Yohn, Newport, PA US
Patent application number | Description | Published |
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20090325407 | SURFACE MOUNT ELECTRICAL CONNECTOR HAVING FLEXIBLE SOLDER TAILS - An electrical connector includes a housing having a mating end and a board end. The housing has a plurality of contact cavities extending along a longitudinal axis between the mating and board ends. A plurality of contacts are received within the contact cavities. The contacts have a mating end and a mounting end, and the contacts have a flexible tail at the mounting end. The tail has a first portion extending along the longitudinal axis and a second portion angled with respect to the first portion with the second portion having a board mounting surface configured to mount to a circuit board. The tail includes a slot open along the board mounting surface. | 12-31-2009 |
20100112847 | CONNECTOR SYSTEM HAVING A VIBRATION DAMPENING SHELL - A connector system is provided that includes electrical connectors, a substrate and a vibration dampening shell. The connectors each have first and second sides. The substrate has an upper surface with the connectors mounted thereon. The shell limits movement of the connectors with respect to one another and is coupled to the first sides of the connectors to limit the movement of the connectors toward and away from the upper substrate. The shell also is coupled to the second sides of the connectors to limit the movement of the connectors in directions transverse to the upper substrate surface. | 05-06-2010 |
Brent David Yohn, Newport, PA US
Patent application number | Description | Published |
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20080252158 | TORQUE RESISTANT TERMINAL BLOCK ASSEMBLY - A power terminal having a unitary connector body. The body includes at least one opening therethrough. The opening is configured to receive an electrically conductive member. The body further includes a recess configured to receive a cap portion of the electrically conductive member. The connector body has an electrically insulative coating on at least a portion of a surface thereof. The insulative coating provides sufficient electrical insulation to substantially prevent electrical communication between the electrically conductive member and the connector body. A method for fabricating a power terminal is also provided. | 10-16-2008 |
20080274645 | HIGH POWER TERMINAL BLOCK ASSEMBLY - A power terminal and a method for making a power terminal having an electrically insulated connector body. A terminal insert is incorporated into the connector body and has at least one threaded electrically conductive member engaged with the terminal insert. The conductive member also includes a cap portion. The terminal insert is formed from a substantially rigid material and is configured to resist torque and pull out forces provided to the conductive member. | 11-06-2008 |
20090177070 | CATHETER TIP ELECTRODE ASSEMBLY AND METHOD FOR FABRICATING SAME - An electrode assembly for a sensor catheter tip includes a first electrode and a second electrode each having a central axis. The two electrodes are axially aligned and spaced apart along the axis. Each of the first and second electrodes comprises a contact aperture spaced from the center axis, and a contact. element positioned within each of the contact apertures. The center axis of each of the first and second electrodes is substantially aligned, and the contact elements corresponding to each of the first and second electrodes are offset, thereby providing staggered contact points for each respective electrode. | 07-09-2009 |
20090203259 | HIGH-SPEED BACKPLANE CONNECTOR - A terminal module for assembly into a high-speed electrical connector having a contact receiving first contact pair and second contact pair, the second contact pair being in electrical communication with the first contact pair via a corresponding pair of contact interconnections. The contact interconnections have a substantially identical length of the corresponding pair and are arranged within parallel planes. The module further includes a shielding member arranged and disposed in close proximity to at least three edges of one or more of the first contact pair, the second contact pair and the contact interconnections to provide shielding. A housing member is arranged and disposed to receive backplane contacts via contact receiving apertures. The housing member is engaged with the first contact pair to receive the contacts into the contacts of the first contact pair. A backplane having grounding plate grid is also disclosed. | 08-13-2009 |
20120045175 | PLUG ASSEMBLY - A plug assembly includes a circular plug shell having a cavity configured to receive a modular plug connector therein. The circular plug shell is configured to be threadably coupled to a corresponding circular jack shell. An insert is loaded into the cavity or the circular plug shell. The insert includes an adapter having a one or two piece body having a circular geometry. The body has a connector chamber configured to hold the modular plug connector therein. | 02-23-2012 |
20130337671 | LATCH ASSEMBLIES FOR CONNECTOR SYSTEMS - A connector system includes a base mount and a slider latch received in the base mount. The slider latch has a profiled groove configured to latchably receive a cam of a connector module. A faceplate is coupled to the base mount. The faceplate has an opening providing access to the slider latch. An ejector button is operatively coupled to the slider latch to move the slider latch from a latched position to an unlatched position. The slider latch is configured to eject the connector module as the slider latch moves between the latched and unlatched positions. A spring engages the slider latch and acts on the slider latch in a biasing direction. The spring forces the slider latch to return to the latched position after the ejector button is released. | 12-19-2013 |
20150031228 | QUICK CONNECT POWER CONNECTOR - An electrical connector for connecting to a terminal post. A contact is provided in electrical engagement with the terminal post regardless of the orientation of the contact with respect to the terminal post. A locking slide is moveably mounted to the housing body. A first reference member is provided on a first end of the body of the connector, the first reference member is provided proximate a first sidewall of the body of the connector. A second reference member is provided on the first end of the body of the connector, the second reference member is provided proximate a second sidewall of the body of the connector. When the locking slide is in the prelocked position, the first reference member is visible and when the locking slide is in the locked position, the second reference member is visible. | 01-29-2015 |
Christopher Yohn, San Diego, CA US
Patent application number | Description | Published |
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20120322157 | STRESS-INDUCED LIPID TRIGGER - The present disclosure provides novel proteins that when over expressed in algae result in an increase or change in fatty acid and/or glycerol lipid production and/or accumulation, without a substantial decrease in the growth rate of the alga or the break down of algal components, such as chlorophyll. The present disclosure also describes methods of using the novel proteins to increase or change the production and/or accumulation of fatty acids and/or glycerol lipids in algae. In addition, these proteins are useful tools in obtaining information about the fatty acid and triacyglyceride (TAG) synthetic pathways in algae. | 12-20-2012 |
20150059023 | BIOMASS YIELD GENES - The present disclosure provides several novel genes that have been shown to increase the biomass yield or biomass of a photosynthetic organism. The disclosure also provides methods of using the novel genes and organisms transformed with the novel genes. | 02-26-2015 |
20150089690 | SODIUM HYPOCHLORITE RESISTANT GENES - The present disclosure provides novel genes, identified from a | 03-26-2015 |
Judge Yohn US
Patent application number | Description | Published |
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20130132061 | JUST-IN-TIME STATIC TRANSLATION SYSTEM FOR EMULATED COMPUTING ENVIRONMENTS - A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit. The computing system includes a linker configured to manage association of at least one of the one or more translated memory banks to the interface layer for native execution by the programmable circuit in place of a corresponding bank of non-native instructions. | 05-23-2013 |
20130132063 | SYSTEMS AND METHODS FOR DEBUGGING JUST-IN-TIME STATIC TRANSLATION IN AN EMULATED SYSTEM - Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system. | 05-23-2013 |
Judge William Yohn, River Falls, WI US
Patent application number | Description | Published |
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20140130026 | OPERAND AND LIMITS OPTIMIZATION FOR BINARY TRANSLATION SYSTEM - Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks. | 05-08-2014 |
Russell Yohn, Shelby Township, MI US
Patent application number | Description | Published |
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20160129535 | WORKPIECE POSITIONING APPARATUS, AND METHOD OF USING SAME - A workpiece positioner is includes a main positioner body including first and second end plate members. The main positioner body also includes a pair of tubular structural members extending between and interconnecting the end plate members, a number of substantially co-planar panel sections disposed between the first and second end plate members, and a number of spaced-apart reinforcing ribs interspersed between the panel sections, the reinforcing ribs also disposed between and interconnecting the tubular structural members. Each of the reinforcing ribs has two opposite side edges, each formed with an arcuate outline shape. The workpiece positioner may also include two or four workpiece support arms attached to the main positioner body, where each of the support arms may have a workpiece-supporting turntable mounted thereon, and may further include first and second shield members attached to the respective tubular members. | 05-12-2016 |
William Judge Yohn, River Falls, WI US
Patent application number | Description | Published |
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20090319837 | Verification of a data processing system using overlapping address ranges - Verifying operation of a data processing system. A first sequence of addressing ranges is generated for multiple requesters. Each addressing range includes a start and an end address and a respective identifying number. A second sequence of verification ranges is generated corresponding the addressing ranges of the first sequence. Each verification range includes a start and an end address and specifies at least one allowed value including each respective identifying number of all of the addressing ranges that overlap the verification range. A respective accessing activity executing on each requestor accesses each addressing range in the first sequence. The accesses include writing the respective identifying number of the addressing range to at least one address of the addressing range. A verification activity executing on a requestor reads a value from each address of each verification range of the second sequence and outputs an error message in response to the value not matching the allowed value. | 12-24-2009 |
20120151144 | METHOD AND SYSTEM FOR DETERMINING A CACHE MEMORY CONFIGURATION FOR TESTING - A method and computer device for determining the cache memory configuration. The method includes allocating an amount of cache memory from a first memory level of the cache memory, and determining a read transfer time for the allocated amount of cache memory. The allocated amount of cache memory then is increased and the read transfer time for the increased allocated amount of cache memory is determined. The allocated amount of cache memory continues to be increased and the read transfer time determined for the each allocated amount until all of the cache memory in all of the cache memory levels has been allocated. The cache memory configuration is determined based on the read transfer times from the allocated portions of the cache memory. The determined cache memory configuration includes the number of cache memory levels and the respective capacities of each cache memory level. | 06-14-2012 |