Patent application number | Description | Published |
20100225609 | TOUCH PANEL, TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage. | 09-09-2010 |
20100225860 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines. A plurality of pixel regions are formed by crossing of the plurality of gate lines and the plurality of data lines, a pixel electrode and a thin film transistor are provided for each pixel region, and one common electrode line is common to two vertically adjacent pixel regions. | 09-09-2010 |
20120099043 | TFT-LCD ARRAY SUBSTRATE, MANUFACTURING METHOD OF THE SAME AND TFT-LCD - According to the embodiments of the invention, a TFT-LCD array substrate, a manufacturing method thereof and a TFT-LCD are provided. The TFT-LCD array substrate comprises: a gate line; a gate line test line; a gate line test terminal; a gate line drive circuit connected to the gate line; and a test TFT. A gate electrode and a drain electrode of the test TFT are connected to the gate line test line, a source electrode of the test TFT is connected to the gate line, and the gate line test terminal is connected to the gate line test line. | 04-26-2012 |
20120241712 | Resistive-Switching Memory and Fabrication Method Thereof - The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved. | 09-27-2012 |
20120243085 | THREE DIMENSIONAL DISPLAY DEVICE AND THREE DIMENSIONAL DISPLAY SYSTEM - Embodiments of the disclosed technology provide a three dimensional (3D) display device, comprising: an optical lens group, display panels, and a display plane, wherein the display panels comprises a first display panel and a second display panel for emitting image light with different polarization states, and wherein the optical lens group is used to refract polarized light emitted from the first and second display panels onto the display plane, so that the image light emitted from the first and second display panels forms images on the display plane. In addition, a 3D display system comprising the above 3D display device is also provided. | 09-27-2012 |
20120289004 | FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR - The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device. | 11-15-2012 |
20130069031 | MULTILEVEL RESISTIVE MEMORY HAVING LARGE STORAGE CAPACITY - The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta | 03-21-2013 |
20130217199 | METHOD FOR FABRICATING RESISTIVE MEMORY DEVICE - The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent. | 08-22-2013 |
20140162415 | TOUCH PANEL, TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage. | 06-12-2014 |
20140306173 | RESISTIVE MEMORY AND METHOD FOR FABRICATING THE SAME - A resistive memory having a leakage inhibiting characteristic and a method for fabricating the same, which can suppress a sneak current in a large scaled crossing array of a RRAM. A memory cell forming the resistive memory comprises a lower electrode, a first semiconductor-type oxide layer, a resistive material layer, a second semiconductor-type oxide layer and an upper electrode which are sequentially stacked. Each of the semiconductor-type oxide layers may be a semiconductor-type metal oxide or a semiconductor-type non-metal oxide. The sneak current may be effectively reduced by means of a Schottky barrier formed between the semiconductor-type oxide layer and the metal electrode, the fabrication process is easy to be implemented, and a high device integration degree can be achieved. | 10-16-2014 |
20150021539 | RESISTIVE MEMORY WITH SMALL ELECTRODE AND METHOD FOR FABRICATING THE SAME - Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO | 01-22-2015 |