Patent application number | Description | Published |
20130286395 | Tool Induced Shift Reduction Determination for Overlay Metrology - One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements. | 10-31-2013 |
20140017604 | LITHOGRAPHY PROCESS - A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer. | 01-16-2014 |
20140240703 | Overlay Sampling Methodology - One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface. | 08-28-2014 |
20140240706 | OVERLAY SAMPLING METHODOLOGY - A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies. | 08-28-2014 |
20150016943 | Lithographic Overlay Sampling - Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure. | 01-15-2015 |
20150042994 | PAIRED EDGE ALIGNMENT - Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs. | 02-12-2015 |
20150058817 | Semiconductor Overlay Production System and Method - Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design. | 02-26-2015 |
20150302127 | Semiconductor Overlay Production System and Method - Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design. | 10-22-2015 |
20160025650 | OVERLAY METROLOGY METHOD AND OVERLAY CONTROL METHOD AND SYSTEM - The present disclosure provides an overlay metrology method, an overlay control method and an overlay control system. The overlay metrology method includes capturing a current layer image of a current overlay mark on a current layer with a current focal length and capturing a previous layer image of a previous overlay mark on a previous layer with a previous focal length. Then, the overlay metrology method further includes combining the current layer image with the previous layer image to form an overlay mark image and determining an overlay error between the current overlay mark and the previous overlay mark based on the overlay mark image. | 01-28-2016 |
20160033878 | OVERLAY SAMPLING METHODOLOGY - One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface. | 02-04-2016 |
Patent application number | Description | Published |
20160094532 | METHOD AND SYSTEM FOR COMMUNICATION CONTROL - The present disclosure relates to a method for communication control, comprising: receiving, from a second user, a request for communicating with a first user, the request including a first identification specific to the first user, the first identification being different from an account used by the first user in the communication; determining, based on a communication mapping associated with the first user, whether the second user is allowed to communicate with the first user using the first identification, the communication mapping indicating authorized users allowed to communicate with the first user and respective identifications allowed to be used by the authorized users; and obtaining, in response to determining that the second user is allowed to communicate with the first user using the first identification, the account used by the first user in the communication to initiate the communication with the first user. | 03-31-2016 |
20160094562 | METHOD AND SYSTEM FOR COMMUNICATION CONTROL - The present disclosure relates to a method for communication control, comprising: receiving, from a second user, a request for communicating with a first user, the request including a first identification specific to the first user, the first identification being different from an account used by the first user in the communication; determining, based on a communication mapping associated with the first user, whether the second user is allowed to communicate with the first user using the first identification, the communication mapping indicating authorized users allowed to communicate with the first user and respective identifications allowed to be used by the authorized users; and obtaining, in response to determining that the second user is allowed to communicate with the first user using the first identification, the account used by the first user in the communication to initiate the communication with the first user. | 03-31-2016 |
Patent application number | Description | Published |
20090122921 | METHOD AND APPARATUS OF DECODING ENCODED DATA FRAME HAVING DUMMY BIT SEQUENCES INCLUDED THEREIN - A method of decoding an encoded data frame including dummy bit sequences each generated from encoding a predetermined bit pattern is provided. The method includes: determining a boundary of dummy bit sequences in the encoded data frame; and generating a decoded data frame according to a partial decoding result and a plurality of predetermined bit patterns each corresponding to one of the dummy bit sequences within the boundary, wherein the partial decoding result is generated by decoding encoded bits beyond the boundary according to the predetermined bit pattern. | 05-14-2009 |
20100183091 | METHOD FOR TUNING A DIGITAL COMPENSATION FILTER WITHIN A TRANSMITTER, AND ASSOCIATED DIGITAL COMPENSATION FILTER AND ASSOCIATED CALIBRATION CIRCUIT - A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistance-capacitance (RC) detection result by performing RC detection on the portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein, wherein the RC detection result corresponds to a detected value representing a product of a resistance value and a capacitance value, and the digital compensation filter includes a gain compensation module and an RC compensation module; and tuning the digital compensation filter by respectively inputting the loop gain calibration result and the RC detection result into the gain compensation module and the RC compensation module. An associated digital compensation filter and an associated calibration circuit are also provided. | 07-22-2010 |
20120057653 | METHOD FOR TUNING A DIGITAL COMPENSATION FILTER WITHIN A TRANSMITTER, AND ASSOCIATED DIGITAL COMPENSATION FILTER - A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one resistance-capacitance (RC) detection result, wherein the digital compensation filter includes an RC compensation module; and tuning the digital compensation filter by inputting the RC detection result into the RC compensation module. For example, the RC detection result may correspond to a detected value representing a product of a resistance value and a capacitance value. In another example, the at least one RC detection result may be obtained by performing RC detection on at least a portion of the transmitter without individually measuring resistance values of resistors therein and capacitance values of capacitors therein. An associated digital compensation filter and an associated calibration circuit are also provided. | 03-08-2012 |
20140062193 | Power Management Method and Power Management System - A power management method includes: reading the driving current; determining if a driving current of an electronic device is less than or equal to a first steady current value for a first period of time; turning off a first electronic module to decrease the driving current when the driving current is less than or equal to the first steady current value for the first period of time; determining if the driving current is within a first judging range for a second period of time; updating the first steady current value with a second steady current value when the driving current is within the first judging range for the second period of time; determining if the second steady current value is less than or equal to an energy saving set value. | 03-06-2014 |
Patent application number | Description | Published |
20120018340 | DEVICE HOUSING AND METHOD FOR MAKING THE SAME - A device housing is provided. The device housing includes a substrate, a silicon dioxide film formed on the substrate, and a zinc oxide film formed on the silicon dioxide film. The silicon dioxide film has micrometer sized structures. The zinc oxide film has nanometer sized structures. A method for making the device housing is also described there. | 01-26-2012 |
20120090868 | HOUSING AND METHOD FOR MAKING THE SAME - A housing for an electronic device includes a metal substrate and a luminous layer formed on the metal substrate, the luminous layer mainly comprises ZnO mixed with In. The disclosure also described a method to make the housing. | 04-19-2012 |
20120164435 | COATED ARTICLE AND METHOD OF MAKING THE SAME - A coated article includes a bonding layer, a chromium oxynitride layer a boron nitride layer formed on a substrate in that order. The boron nitride layer is made of hexagonal structure boron nitride. | 06-28-2012 |
20120196148 | COATED ARTICLE AND METHOD OF MAKING THE SAME - A coated article includes a magnesium layer, a magnesium oxynitride layer a titanium nitride layer formed on a substrate in that order. The substrate is made of magnesium alloy. | 08-02-2012 |
20120244382 | COATED ARTICLE AND METHOD OF MAKING THE SAME - A coated article includes a bonding layer, an iridium layer, a chromium oxynitride layer and a chromium nitride layer formed on a substrate in that order. The substrate is made of die steel. | 09-27-2012 |
20120276407 | PROCESS FOR SURFACE TREATING IRON-BASED ALLOY AND ARTICLE - A process for surface treating iron-based alloy includes providing a substrate made of iron-based alloy. A stainless steel layer is then formed on the substrate by sputtering. A silicon-oxygen-nitrogen layer is formed on the stainless steel layer by sputtering. A boron-nitrogen layer is next formed on the silicon-oxygen-nitrogen layer by sputtering. | 11-01-2012 |
20120276408 | PROCESS FOR SURFACE TREATING IRON-BASED ALLOY AND ARTICLE - A process for surface treating iron-based alloy includes providing a substrate made of iron-based alloy. A chromium layer is then formed on the substrate by vacuum sputtering. A silicon oxide layer, an alumina layer, and a boron nitride layer are formed in that order by vacuum evaporation. | 11-01-2012 |
20120276413 | PROCESS FOR SURFACE TREATING IRON-BASED ALLOY AND ARTICLE - A process for surface treating iron-based alloy includes providing a substrate made of iron-based alloy. A chromium-oxygen-nitrogen layer is then formed on the substrate by sputtering. An iridium layer is formed on the chromium-oxygen-nitrogen layer by sputtering. A boron-nitrogen layer is next formed on the iridium layer by sputtering. | 11-01-2012 |
20120315501 | COATED ARTICLE AND METHOD FOR MAKING SAME - A coated article is provided. A coated article includes a substrate having a color layer and a ceramic layer formed thereon, and in that order. The color layer substantially comprises a material elected from the group consisting of aluminum, aluminum alloy, zinc, and zinc alloy. The ceramic layer substantially consists of substance M, elemental O, and elemental N, wherein M is elemental Al or elemental Zn. | 12-13-2012 |
20130029097 | COATED ARTICLE AND METHOD FOR MAKING SAME - A coated article includes a substrate, a first layer deposited on the substrate, a second layer deposited on the first layer and a third layer deposited on the second layer. The first layer substantially consists of one material selected from the group consisting of Al layer, Al alloy layer, Zn layer or Zn alloy layer. The first layer is white. The second layer substantially includes metal M′, O and N, wherein M′ is Al or Zn. The third layer is an aluminum oxide layer or a silicon oxide layer. The third layer has an anti-fingerprint property. | 01-31-2013 |
Patent application number | Description | Published |
20160028386 | DELAY CIRCUIT - A delay circuit includes a current circuit, a first current mirror circuit, a second current mirror circuit, a self-compensation circuit, and a delay capacitor. A fixed ratio is between the first current and the second current provided by the current circuit. The first current mirror circuit generates a first mirror current in response to the first current. A partial current of the second current flowing through the second current mirror circuit is a base current, and the second current mirror circuit generates a second mirror current in response to the base current. The self-compensation circuit generates a feedback current in response to the second mirror current. The delay capacitor generates a delay signal. The charging current is equal to the second current subtracting the base current. The first mirror current is the sum of the base current, the second mirror current, and the feedback current. | 01-28-2016 |
20160048148 | LOW-DROPOUT VOLTAGE REGULATOR - The invention is directed to a low-dropout voltage regulator (LDO), including a power transistor, a driving stage circuit, a feedback circuit, a bias power source and an auxiliary reference current generation circuit. The power transistor is controlled by a driving signal to convert an input voltage into an output voltage. The feedback circuit generates a feedback voltage according to the output voltage. The driving stage circuit generates the driving signal according to the feedback voltage and the reference voltage. The bias power source provides a bias current. The auxiliary reference current generation circuit is configured to sample an output current, adjust the sampled output current to generate an adjustment current by means of mapping and superpose the adjustment current onto the bias current to generate a reference current to control drive capability of the driving stage circuit. | 02-18-2016 |