Ying-Shiou
Ying-Shiou Chen, Taipei City TW
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20110155974 | Near Infrared Absorbing Agent and Near Infrared Absorbing Film - Disclosed herein is a method for preparing a near infrared absorbing agent. The method includes admixing tungsten trioxide and a reducing agent in water and allowing for a partial reduction of the tungsten trioxides to yield the near infrared absorbing agent. | 06-30-2011 |
20120305864 | Near Infrared Absorbing Agent and Near Infrared Absorbing Film - Disclosed herein is a method for preparing a near infrared absorbing agent. The method includes admixing tungsten trioxide and a reducing agent in water and allowing for a partial reduction of the tungsten trioxides to yield the near infrared absorbing agent. | 12-06-2012 |
Ying-Shiou Lin, Hsinchu City TW
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20080290412 | SUPPRESSING SHORT CHANNEL EFFECTS - An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate. | 11-27-2008 |
Ying-Shiou Lin US
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20120217579 | High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region. | 08-30-2012 |
Ying-Shiou Lin, Chiayi TW
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20130256846 | Semiconductor Overlapped PN Structure and Manufacturing Method Thereof - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 10-03-2013 |