Patent application number | Description | Published |
20100317299 | SYSTEM AND METHOD FOR ADJACENT CHANNEL POWER DETECTION AND DYNAMIC BANDWIDTH FILTER CONTROL - A system for detecting and minimizing interference in a radio receiver includes a plurality of bandpass filters having different response characteristics, a power detector configured to compare a power output of a first bandpass filter and a second bandpass filter, and logic to cascade a third bandpass filter when the difference in power output between the power output of the first bandpass filter and the power output of the second bandpass filter exceeds a threshold amount. | 12-16-2010 |
20120139635 | Gate-Based Output Power Level Control Power Amplifier - A gate power control technique for a power amplifier (PA) provides practical improved efficiency at backed-off power levels. It can be applied to the main gate of the output stage of the PA, the cascode gate, or any combination thereof. Both voltage mode and current mode signal processing may be used. The gate power control can be implemented in both open-loop and closed-loop using AC and DC coupled drivers and output stages. It may further use one or more control ports in the radio frequency (RF) signal path. | 06-07-2012 |
20120142284 | SYSTEM AND METHOD FOR ADJACENT CHANNEL POWER DETECTION AND DYNAMIC BANDWIDTH FILTER CONTROL - A system for detecting and minimizing interference in a radio receiver includes a plurality of bandpass filters having different response characteristics, a power detector configured to compare a power output of a first bandpass filter and a second bandpass filter, and logic to cascade a third bandpass filter when the difference in power output between the power output of the first bandpass filter and the power output of the second bandpass filter exceeds a threshold amount. | 06-07-2012 |
20120225629 | SYSTEM AND METHOD FOR TUNING A RADIO RECEIVER - A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency. | 09-06-2012 |
20140030990 | Methods and Circuits for Detuning a Filter and Matching Network at the Output of a Power Amplifier - In transmitter modules or power amplifier (PA) modules there is at least a possible path for a second and even a third harmonic of a low band to crossover unfiltered into the high band path and reach the antenna and hence cross band isolation is necessary. Forward isolation is necessary in order to limit the input crossing over the PAs into the antenna port. According to the methods and the circuits such cross band isolation and forward isolation is improved by detuning the filter and matching network at the output of the PA. The circuit comprises a trap at the harmonic frequencies of the low band thereby at least reducing the impacts of the cross band and forward isolation. | 01-30-2014 |
20140049321 | SYSTEMS, CIRCUITS AND METHODS RELATED TO CONTROLLERS FOR RADIO-FREQUENCY POWER AMPLIFIERS - Disclosed are systems, circuits and methods related to controlling of a radio-frequency (RF) power amplifier (PA). In some embodiments, a PA control circuit can include a first circuit configured to generate a replica base current from a base current provided to the PA, with the replica base current being representative of a collector current of the PA scaled by a beta parameter. The PA control circuit can further include a second circuit configured to generate a beta-tracking reference current from a temperature-compensated voltage and a base resistance associated with the PA. The PA control circuit can further include a current steering circuit configured to receive the replica base current and the beta-tracking reference current and generate a proportional current to a clamping node of a base driver. In some embodiments, the replica base current can be obtained by a current-mode comparison of a finger-sensed current with a ramp current. | 02-20-2014 |
20150148095 | MULTI-MODE POWER AMPLIFIER - A power amplifier module that includes a power amplifier and a controller is presented herein. The power amplifier module may include a set of transistor stages and a plurality of bias circuits. At least one transistor stage from the set of transistor stages may be in electrical communication with a first bias circuit and a second bias circuit from the plurality of bias circuits. The first bias circuit can be configured to apply a first bias voltage to the at least one transistor stage and the second bias circuit can be configured to apply a second bias voltage to the at least one transistor stage. The controller may be configured to activate one of the first bias circuit and the second bias circuit. | 05-28-2015 |
Patent application number | Description | Published |
20100264991 | SWITCHED CAPACITOR VOLTAGE CONVERTER FOR A POWER AMPLIFIER - A voltage converter includes a plurality of capacitors and corresponding first switch elements, the capacitors coupled in series and arranged to each charge to a voltage level during a first clock period, the voltage level determined by a supply voltage level, the number of capacitors and a value of each capacitor; and a plurality of second switch elements configured to cause the plurality of capacitors to be connected in parallel and to discharge into an output capacitor during a second clock period, the output capacitor charged to a discrete voltage output level so that the output capacitor provides the discrete voltage output level, wherein the discrete voltage output level is less than the supply voltage level and wherein the discrete voltage output level is used to develop a bias signal that is supplied to a power amplifier element. | 10-21-2010 |
20120092075 | POWER AMPLIFICATION SYSTEMS AND METHODS - A power amplifier system includes a power amplifier element that provides a power output signal in response to a bias signal, and a voltage converter. The voltage converter provides at least one discrete voltage output level to the power amplifier element, where the discrete voltage output level is used to develop the bias signal. | 04-19-2012 |
20140266432 | AMPLIFIER PHASE DISTORTION CORRECTION BASED ON AMPLITUDE DISTORTION MEASUREMENT - This application discloses correction circuitry for correcting a phase distortion in an amplification circuit by measuring an amplitude distortion and controlling a phase shifting component based upon the measured amplitude distortion. In one embodiment, a first amplitude distortion sensor is coupled to a first node of an amplification circuit, and a first phase shifter is coupled to a second node of the amplification circuit. Additionally, a first control circuit is coupled to the first amplitude sensor and to the first phase shifter. The first control circuit is configured to correlate a first amplitude distortion measured by the first amplitude distortion sensor to a first inferred phase distortion, and to generate a first phase correction signal based upon the first inferred phase distortion, and is configured to send the first phase correction signal towards the first phase shifter. | 09-18-2014 |
Patent application number | Description | Published |
20080214134 | System And Method For Adjacent Channel Power Detection And Dynamic Bandwidth Filter Control - A system for detecting and minimizing interference in a radio receiver includes a plurality of bandpass filters having different response characteristics, a power detector configured to compare a power output of a first bandpass filter and a second bandpass filter, and logic to cascade a third bandpass filter when the difference in power output between the power output of the first bandpass filter and the power output of the second bandpass filter exceeds a threshold amount. | 09-04-2008 |
20090197554 | System And Method For Station Detection And Seek In A Radio Receiver - A system for detecting a broadcast channel in a radio receiver includes a receive signal strength indicator (RSSI) element configured to develop an RSSI signal that is representative of a power in a desired channel, a switchable bandwidth channel select filter having a power detector configured to compare a power output of the desired channel and at least one channel adjacent to the desired channel to develop a signal to adjacent channel power ratio (SACPR) signal that is representative of the noise in the desired channel, and a seek element configured to determine whether the RSSI signal is greater than a predetermined RSSI threshold and configured to determine whether the SACPR signal is greater than a predetermined SACPR threshold. | 08-06-2009 |
20090238312 | System And Method For Tuning A Radio Receiver - A system for tuning a radio receiver includes a radio receiver configured to provide a downconverted digital error signal, a digital synthesizer circuit configured to generate a first local oscillator control signal, a digital automatic frequency control (AFC) circuit configured to generate a second local oscillator control signal, wherein the digital synthesizer circuit is enabled to generate the first local oscillator control signal when the digital AFC circuit is disabled, the first local oscillator control signal corresponds to an estimate of a desired local oscillator frequency, the digital AFC circuit is enabled to generate the second local oscillator control signal when the digital synthesizer circuit is disabled and the second local oscillator control signal corresponds to the desired local oscillator frequency. | 09-24-2009 |
Patent application number | Description | Published |
20150339430 | VIRTUAL HIERARCHICAL LAYER USAGE - Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes. | 11-26-2015 |
20150339433 | VIRTUAL CELL MODEL USAGE - Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created. | 11-26-2015 |
20150339434 | VIRTUAL HIERARCHICAL LAYER PROPAGATION - Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations. | 11-26-2015 |