Patent application number | Description | Published |
20100258868 | INTEGRATED CIRCUIT SYSTEM WITH A FLOATING DIELECTRIC REGION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer. | 10-14-2010 |
20100304556 | INTEGRATED CIRCUIT SYSTEM WITH VERTICAL CONTROL GATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a mesa over a substrate; forming a trench in the substrate adjacent the mesa; forming a second gate and a charge storage material along a trench sidewall; and forming a first gate from the mesa. | 12-02-2010 |
20110044115 | Non-volatile memory using pyramidal nanocrystals as electron storage elements - A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. | 02-24-2011 |
20110115009 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 05-19-2011 |
20110156121 | MEMORY CELL WITH IMPROVED RETENTION - A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals. | 06-30-2011 |
20120007180 | FinFET with novel body contact for multiple Vt applications - FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications. | 01-12-2012 |
20120007185 | Novel method to tune narrow width effect with raised S/D structure - A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width. | 01-12-2012 |
20120038009 | Novel methods to reduce gate contact resistance for AC reff reduction - A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff. | 02-16-2012 |
20120119281 | INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF - A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess. | 05-17-2012 |
20120146160 | HIGH-K METAL GATE DEVICE - A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer. | 06-14-2012 |
20120168895 | MODIFYING GROWTH RATE OF A DEVICE LAYER - A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate. | 07-05-2012 |
20130328118 | NON-VOLATILE MEMORY USING PYRAMIDAL NANOCRYSTALS AS ELECTRON STORAGE ELEMENTS - A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices. | 12-12-2013 |
20140151775 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 06-05-2014 |
20140332902 | NOVEL METHOD TO TUNE NARROW WIDTH EFFECT WITH RAISED S/D STRUCTURE - A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width. | 11-13-2014 |
Patent application number | Description | Published |
20120230564 | OBTAINING DATA FOR AUTOMATIC GLAUCOMA SCREENING, AND SCREENING AND DIAGNOSTIC TECHNIQUES AND SYSTEMS USING THE DATA - A non-stereo fundus image is used to obtain a plurality of glaucoma indicators. Additionally, genome data for the subject is used to obtain genetic marker data relating to one or more genes and/or SNPs associated with glaucoma. The glaucoma indicators indicators and genetic marker data are input into an adaptive model operative to generate an output indicative of a risk of glaucoma in the subject. In combination, the genetic indicators and genome data are more informative about the risk of glaucoma than either of the two in isolation. The adaptive model may be a two-stage model, having a first stage in which individual genetic indicators are combined with respective portions of the genome data by first adaptive model modules to form respective first outputs, and a second stage in which the first outputs are combined by a second adaptive mode. Texture analysis is performed on the fundus images to classify them based on their quality, and only images which are determined to meet a quality criterion are subjected to an analysis to determine if they exhibit glaucoma indicators. Also, the images are put into a standard format. The system may include estimating the position of the optic cup by combining results from multiple optic cup segmentation techniques. The system may include estimating the position of the optic disc by applying edge detection to the funds image, excluding edge points that are unlikely to be optic disc boundary points, and estimating the position of an optic disc by fitting an ellipse to the remaining edge points. | 09-13-2012 |
20130196300 | ROBOT ASSISTED SURGICAL TRAINING - A surgical training system and method. The system comprises means for recording reference data representing a reference manipulation of a computer generated model of an object by a master user; means for physically guiding a trainee user based on the recorded reference data during a training manipulation of the model of the object by the trainee user; and means for recording assessment data representing an assessment manipulation of the model of the object by the trainee user without guidance. | 08-01-2013 |
20130224710 | ROBOTIC DEVICE FOR USE IN IMAGE-GUIDED ROBOT ASSISTED SURGICAL TRAINING - A robotic device for use in image-guided robot assisted surgical training, the robotic device comprising a manual interface structure configured to simulate handling of a surgical tool; a translational mechanism for translational motion of the manual interface structure; a rotational mechanism for rotational motion of the manual interface structure; and a spherical mechanism configured to decouple the orientation of the manual interface structure into spatial coordinates, wherein a linkage between the rotational mechanism, the rotational mechanism and the spherical mechanism, and the manual interface structure are disposed on opposing sides of an intersection of a pitch axis and a yaw axis of the spherical mechanism. | 08-29-2013 |