Patent application number | Description | Published |
20090167306 | FOLDED GRADIENT TERMINAL BOARD END CONNECTOR - A folded gradient terminal board end connector includes a multi-layer terminal connection board having a plurality of connection paths and vias configured to provide intercrossing between a plurality of folded gradient coils and further to provide symmetry between the plurality of folded gradient coils without spatial interference between folded portions of the plurality of folded gradient coils to optimize the folded gradient coil efficiency. | 07-02-2009 |
20100148779 | TRANSVERSE GRADIENT COIL FOR MRI SYSTEMS AND METHOD FOR MANUFACTURING THE SAME - A transverse gradient coil for an MRI system is provided. The transverse gradient coil comprises a first coil layer; and an insulation layer made of thermoplastic insulation resin which has a thermal conductivity greater than 1.5 W/m·K, the insulation layer having one side bonded to the first coil layer. A method for manufacturing the transverse gradient coil by injection molding or compression molding is also provided. | 06-17-2010 |
20100148903 | ELECTRICAL ENERGY TRANSFORMATION APPARATUS - In one aspect, the present invention provides a high voltage-high frequency electrical energy transformation apparatus comprising a frequency inverter capable of converting 60 Hz electrical energy into 40-100 KHz electrical energy; and a voltage transformer. The voltage transformer comprises a transformer housing; at least one soft magnetic core; a low voltage primary winding and a high voltage secondary winding; and a solid insulating material comprising polydicyclopentadiene. The solid insulating material is in contact with the high voltage secondary winding. | 06-17-2010 |
20100240804 | IN-SITU POLYMERIZED NANOCOMPOSITES - Disclosed herein is a method of making a polymer composite composition comprising blending a polymeric material precursor with nanoparticles, wherein each nanoparticle comprises a substrate and a coating composition disposed on the substrate; and polymerizing the polymeric material precursor to form a polymeric material, wherein the nanoparticles are dispersed within the polymeric material to form a polymer composition. | 09-23-2010 |
20110207863 | COMPOSITE FILMS COMPRISING PASSIVATED NANOPARTICULATED CERAMIC OXIDES - The present invention is directed to high temperature performance filled polyimide materials useful for high power density applications having good ultra high thermal properties. A high temperature dielectric film is disclosed comprising an aromatic polyimide formed by a solution polycondensation reaction and a passivated nanoparticulate ceramic oxide dispersed within the aromatic polyimide. The ceramic oxide nanoparticles are comprised of a monofunctional organosilane covalently attached to the surface of the ceramic oxide nanoparticles. | 08-25-2011 |
20120080970 | HIGH VOLTAGE AND HIGH TEMPERATURE WINDING INSULATION FOR ESP MOTOR - A litz wire includes, in one embodiment, a plurality of twisted strands, wherein one or more of the strands includes a composite magnet wire. The composite magnet wire includes a metal wire having a nanocoating on its outer surface. The nanocoating includes an electrical insulating polyimide matrix and a plurality of alumina nano particles dispersed homegenueoslytherein. The alumina nano particles have a phenyl siloxane surface coating. The litz wire has a temperature index of at least 300° C. as obtained in accordance with either ASTM E1641, ASTM E1877, or ASTM D2307. Motors and ESP assemblies utilizing the litz wire are also disclosed. | 04-05-2012 |
20120152590 | High Temperature High Frequency Magnet Wire and Method of Making - A composite magnet wire includes, in an exemplary embodiment, a metal wire and a coating applied to an outer surface of the wire. The coating includes a polyimide polymer and a plurality of alumina nano particles dispersed in the polyimide polymer. The alumina nano particles have a surface treatment applied to outer surfaces of the alumina nano particles, where the surface treatment includes a phenyl-silane. The composite magnet wire has a thermal degradation temperature index of at least 300° C. as calculated in accordance with ASTM E1641 or D2307. | 06-21-2012 |
20120190233 | ULTRA-LOW CAPACITANCE HIGH VOLTAGE CABLE ASSEMBLIES FOR CT SYSTEMS - The present embodiments relate to a cable assembly with ultra-low capacitance. In one embodiment, a cable assembly is provided. The cable assembly includes an insulation layer. The insulation layer includes a low-permittivity insulation material. | 07-26-2012 |
20120269660 | ELECTRIC MOTOR AND ELECTRIC SUBMERSIBLE PUMP - In accordance with one aspect of the present invention, an electric motor is provided that includes a housing, a stator, and a rotor, wherein the stator and the rotor are disposed within the housing. The housing, the stator, and the rotor define an internal volume within the housing, said internal volume configured to receive a dielectric fluid. The stator includes a winding including an electrical conductor disposed within a porous ceramic insulating layer, said porous ceramic insulating layer being in fluid communication with the internal volume. An electric submersible pump system is also provided. | 10-25-2012 |
20120282120 | ELECTRIC CABLE, ELECTRIC MOTOR AND ELECTRIC SUBMERSIBLE PUMP - In accordance with one aspect of the present invention, an electric motor is provided that includes a housing, a stator, and a rotor, wherein the stator and rotor are disposed within the housing. The housing, the stator, and the rotor define an internal volume within the housing, said internal volume configured to receive a dielectric fluid. The electric motor further includes at least one electric cable configured to electrically power the electric motor, wherein the electric cable includes at least one electrical conductor disposed within at least one protective layer, and wherein the electrical conductor and the protective layer define at least one channel configured to deliver the dielectric fluid to the internal volume. An electric submersible pump system is also provided. | 11-08-2012 |
20130076191 | HYBRID DIELECTRIC FILM FOR HIGH TEMPERATURE APPLICATION - A high-temperature insulation assembly for use in high-temperature electrical machines and a method for forming a high-temperature insulation assembly for insulating conducting material in a high-temperature electrical machine. The assembly includes a polymeric film and at least one ceramic coating disposed on the polymeric film. The polymeric film is disposed over conductive wiring or used as a conductor winding insulator for phase separation and slot liner. | 03-28-2013 |
20130285781 | NANO DIELECTRIC FLUIDS - A system is provided. The system includes about 99.9 Wt % to about 95 Wt % of an insulating liquid, and about 0.1 Wt % to about 5 Wt % of insulating, inorganic, non-magnetic nanoparticles. Another aspect of the invention includes an electrical apparatus. The electrical apparatus includes an insulation system that comprises a dielectric fluid having about 99.9 Wt % to about 95 Wt % of an insulating liquid, and about 0.1 Wt % to about 5 Wt % of insulating, inorganic, non-magnetic nanoparticles. | 10-31-2013 |
20140152155 | HIGH TEMPERATURE DOWNHOLE MOTORS WITH ADVANCED POLYIMIDE INSULATION MATERIALS - An electric motor assembly configured for use in a downhole pumping system includes a number of electrically conductive components that are insulated from fluids, mechanical abrasion, electrical current and electrical grounds using an advanced polyimide film. Preferred polyimide films include poly(4,4′-oxydiphenylene-pyromellitimide) and biphenyl-tetracarboxylic acid dianhydride (BPDA) type polyimide films. Magnet wire, stator laminates, stator coil end turns, motor leads and power cables can all be insulated with the selected polyimide film. | 06-05-2014 |
20140154113 | HIGH TEMPERATURE DOWNHOLE MOTORS WITH ADVANCED POLYIMIDE INSULATION MATERIALS - An electric motor assembly configured for use in a downhole pumping system includes a number of electrically conductive components that are insulated from fluids, mechanical abrasion, electrical current and electrical grounds using an advanced polyimide film. Preferred polyimide films include poly(4,4′-oxydiphenylene-pyromellitimide) and biphenyl-tetracarboxylic acid dianhydride (BPDA) type polyimide films. Magnet wire, stator laminates, stator coil end turns, motor leads and power cables can all be insulated with the selected polyimide film. | 06-05-2014 |
20140238554 | HIGH TEMPERATURE HIGH FREQUENCY MAGNET WIRE AND METHOD OF MAKING - A method of making a composite magnet wire includes mixing alumina nano particles with a polyimide polymer to form a polyimide mixture, the alumina nano particles having a surface treatment applied to outer surfaces of the alumina nano particles, the surface treatment including a phenyl-silane; coating a wire with the polyimide mixture by passing the wire through a coating die; heating the coated wire; cooling the coated wire; passing the coated wire through an annealing oven at a temperature of about 425° C. to about 475° C. at a speed of about 15 to about 30 feet per minute to anneal the coated wire; cooling the annealed coating wire; spooling the coated wire onto a metal spool; heating the spooled wire at about 300° C. to about 400° C. for about 20 to about 40 minutes; and cooling the heated spooled wire. | 08-28-2014 |
20140251504 | PASSIVATION OF HOLLOW COPPER STRANDS IN A STATOR WATER COOLING SYSTEM - A system for passivating a plurality of hollow copper strands in a stator water cooling system including; a first storage tank containing a cleaning solution, a second storage tank containing rinsing water; a third storage tank containing a passivation solution; a plurality of conduits connecting the first, second, and third storage tanks in a closed loop with the plurality of hollow copper strands; and an alkaline pump for pumping the cleaning solution, the rinsing water, and the passivation solution through the closed loop. | 09-11-2014 |
20140353000 | ELECTRICAL INSULATION SYSTEM - A system and a method are presented. The system includes an electrically conducting material and an electrical insulation system. The electrical insulation system includes a layered insulation tape that has a first layer and a second layer. The first layer includes a mica paper and a binder resin in a range from about 5 wt % to about 12 wt % of the insulation tape. The second layer includes a composite of layered nanoparticles dispersed in a polyetheretherketone (PEEK) matrix. The second layer laminates the first layer. The method includes attaching the first layer and the second layer with or without the addition of further resin; using the layered insulation tape as a turn insulation and ground wall insulation for an electrically conducting material; and impregnating the system with a nanofiller-incorporated resin by a vacuum pressure impregnation method, to form an insulation system within the system. | 12-04-2014 |
20150030785 | HYBRID DIELECTRIC FILM FOR HIGH TEMPERATURE APPLICATION - A high-temperature insulation assembly for use in high-temperature electrical machines and a method for forming a high-temperature insulation assembly for insulating conducting material in a high-temperature electrical machine. The assembly includes a polymeric film and at least one ceramic coating disposed on the polymeric film. The polymeric film is disposed over conductive wiring or used as a conductor winding insulator for phase separation and slot liner. | 01-29-2015 |
20150353788 | COMPOSITION FOR BONDING WINDINGS OR CORE LAMINATES IN AN ELECTRICAL MACHINE, AND ASSOCIATED METHOD - A curable composition for bonding windings or core laminates in an electrical machine is presented. The curable composition includes: (A) about 10 weight percent to about 25 weight percent of a polyfunctional cyanate ester; (B) about 35 weight percent to about 65 weight percent of a first difunctional cyanate ester, or a prepolymer thereof; (C) about 15 weight percent to about 40 weight percent of a second difunctional cyanate ester, or a prepolymer thereof. An associated method is also presented. | 12-10-2015 |
20150357086 | CURABLE COMPOSITION FOR ELECTRICAL MACHINE, AND ASSOCIATED METHOD - A curable composition for an electrical machine is presented. The curable composition includes: (A) about 10 weight percent to about 30 weight percent of a polyfunctional cyanate ester; (B) about 25 weight percent to about 60 weight percent of a first difunctional cyanate ester, or a prepolymer thereof; (C) about 10 weight percent to about 30 weight percent of a second difunctional cyanate ester, or a prepolymer thereof, and (D) about 5 weight percent to about 25 weight percent of a thermally conductive filler comprising boron nitride. An associated method is also presented. | 12-10-2015 |
Patent application number | Description | Published |
20120126358 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH - A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 05-24-2012 |
20120302057 | SELF ALIGNING VIA PATTERNING - A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch. | 11-29-2012 |
20130175658 | TONE INVERSION WITH PARTIAL UNDERLAYER ETCH FOR SEMICONDUCTOR DEVICE FORMATION - A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer. | 07-11-2013 |
20130216776 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 08-22-2013 |
20140023834 | IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER - At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer. | 01-23-2014 |
20140024219 | IMAGE TRANSFER PROCESS EMPLOYING A HARD MASK LAYER - At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed. An overlying structure including a second pattern that includes at least one blocking area is formed over said patterned mask layer. Portions of said patterned mask layer that do not underlie said blocking area are removed. The remaining portions of the patterned mask layer include a composite pattern that is an intersection of the first pattern and the second pattern. The patterned mask layer includes a dielectric material or a metallic material, and thus, enables high fidelity pattern transfer into an underlying material layer. | 01-23-2014 |
20140027878 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 01-30-2014 |
20140027917 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140027923 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 01-30-2014 |
20140057436 | THREE PHOTOMASK SIDEWALL IMAGE TRANSFER METHOD - A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer. | 02-27-2014 |
20140110846 | DUAL HARD MASK LITHOGRAPHY PROCESS - A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (OPL), and a first photoresist are applied above the first metallic hard mask layer. A first via pattern is transferred from the first photoresist layer into the second metallic hard mask layer. A second OPL and a second photoresist are applied and patterned with a second via pattern, which is transferred into the second metallic hard mask layer. A first composite pattern of the first and second via patterns is transferred into the at least one dielectric material layer. A second composite pattern that limits the first composite pattern with the areas of the openings in the first metallic hard mask layer is transferred into the interconnect-level dielectric layer. | 04-24-2014 |
20140145295 | DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION - Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping. | 05-29-2014 |
20140199628 | LITHOGRAPHIC MATERIAL STACK INCLUDING A METAL-COMPOUND HARD MASK - A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing. | 07-17-2014 |
20140256139 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 09-11-2014 |
20140256145 | DSA GRAPHO-EPITAXY PROCESS WITH ETCH STOP MATERIAL - A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials. | 09-11-2014 |
20140264596 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140264603 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 09-18-2014 |
20140312433 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140315379 | CONTACT STRUCTURE EMPLOYING A SELF-ALIGNED GATE CAP - After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion. | 10-23-2014 |
20140315380 | TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER - A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure. | 10-23-2014 |
20140346640 | NON-LITHOGRAPHIC HOLE PATTERN FORMATION - A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140349088 | NON-LITHOGRAPHIC LINE PATTERN FORMATION - A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions. | 11-27-2014 |
20140363969 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-11-2014 |
20140374839 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER - A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins. | 12-25-2014 |
20140377917 | SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN FORMED ON BULK AND GATE CHANNEL FORMED ON OXIDE LAYER - A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins. | 12-25-2014 |
20150031201 | TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER - A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure. | 01-29-2015 |
20150035154 | PROFILE CONTROL IN INTERCONNECT STRUCTURES - The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. | 02-05-2015 |
20150048429 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices and sidewall image transfer methods with a spin on hardmask. Methods for forming fins include forming a trench through a stack of layers that includes a top and bottom insulator layer, and a layer to be patterned on a substrate; isotropically etching the top and bottom insulator layers; forming a hardmask material in the trench to the level of the bottom insulator layer; isotropically etching the top insulator layer; and etching the bottom insulator layer and the layer to be patterned down to the substrate to form fins from the layer to be patterned. | 02-19-2015 |
20150048430 | SIDEWALL IMAGE TRANSFER WITH A SPIN-ON HARDMASK - Semiconductor devices include a first and a second set of parallel fins, each set of fins having a same number of fins and a pitch between adjacent fins below a minimum pitch of an associated lithography process, where a spacing between the first and second set of fins is greater than the pitch between adjacent fins; a gate structure over the first and second sets of fins; a merged source region that connects the first and second sets of fins on a first side of the gate structure; and a merged drain region that connects the first and second sets of fins on a second side of the gate structure. | 02-19-2015 |
20150054077 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150054121 | FINFET FORMED OVER DIELECTRIC - A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material. | 02-26-2015 |
20150069625 | ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process. | 03-12-2015 |
20150091181 | SELF-ALIGNED VIAS FORMED USING SACRIFICIAL METAL CAPS - A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric cap in the cap opening and on the metal line; forming an interconnect dielectric layer over the dielectric cap and the second dielectric layer; forming an interconnect opening in the interconnect dielectric layer; removing a portion of the dielectric cap exposed by the interconnect opening selective to the interconnect dielectric layer, the second dielectric layer, and the metal line; and forming an interconnect structure in the interconnect opening, the interconnect structure comprising a contact line above a via, the via having an upper via portion with angled sidewalls and a lower via portion with substantially vertical sidewalls. | 04-02-2015 |
20150108572 | Electrically Isolated SiGe FIN Formation By Local Oxidation - A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein. | 04-23-2015 |
20150140762 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-21-2015 |
20150144886 | FINFET WITH MERGE-FREE FINS - A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions. | 05-28-2015 |
20150145065 | finFET Isolation by Selective Cyclic Etch - Etching interleaved structures of semiconductor material forming fins of finFETs and local isolation material interposed between the fins is performed alternately and cyclically by alternating etchants cyclically such as by alternating gases during reactive ion etching. Etchants are preferably alternated when one of the semiconductor material and the local isolation material protrudes above the other by a predetermined distance. Since protruding surfaces are etched more rapidly than recessed surfaces, the overall etching process is accelerated and completed in less time such that erosion of other materials to which the etchants are less than optimally selective is reduced and allow improved etching of trenches for improved isolation structures to be formed. | 05-28-2015 |
20150179769 | FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES - Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate. | 06-25-2015 |
20150221547 | HARDMASK FACETING FOR ENHANCING METAL FILL IN TRENCHES - A stack of an interlevel dielectric (ILD) layer, a dielectric cap layer, and a metallic hard mask layer is formed on a substrate. The metallic hard mask layer can be patterned with a first pattern. A photoresist layer is formed over the metallic hard mask layer and is patterned with a second pattern. A combination of the first pattern and the second pattern is transferred into the ILD layer to form a dual damascene trench, which includes an undercut underneath the patterned dielectric cap layer. The metallic hard mask layer is removed and the dielectric cap layer is anisotropically etched to form faceted edges and removal of overhanging portions. A metallic material can be deposited into the dual damascene trench without formation of voids during a metal fill process. | 08-06-2015 |
20150228762 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 08-13-2015 |
20150236159 | WORK FUNCTION METAL FILL FOR REPLACEMENT GATE FIN FIELD EFFECT TRANSISTOR PROCESS - A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse. | 08-20-2015 |
20150243513 | FIN DENSITY CONTROL OF MULTIGATE DEVICES THROUGH SIDEWALL IMAGE TRANSFER PROCESSES - Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate. | 08-27-2015 |
20150243760 | LOW-K SPACER FOR RMG FINFET FORMATION - A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess. | 08-27-2015 |
20150255300 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 09-10-2015 |
20150287614 | FINFET SEMICONDUCTOR DEVICE HAVING INTEGRATED SiGe FIN - A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough. | 10-08-2015 |
20150311320 | FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS - A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure. | 10-29-2015 |
20150332977 | ELECTRICALLY ISOLATED SiGe FIN FORMATION BY LOCAL OXIDATION - A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein. | 11-19-2015 |
20150364372 | DOUBLE SELF-ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-17-2015 |
20150371896 | DOUBLE SELF ALIGNED VIA PATTERNING - A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer. | 12-24-2015 |
20160027776 | DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS - A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins. | 01-28-2016 |
20160079384 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 03-17-2016 |