Patent application number | Description | Published |
20080224139 | THIN FILM TRANSISTOR - A thin film transistor including a substrate, a gate, a gate insulator layer, a semiconductor layer, an ohmic contact layer, a source and a drain is provided. The gate is disposed on the substrate while the gate insulator layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulator layer above the gate. The semiconductor layer includes an undoped amorphous silicon layer and a first undoped microcrystalline silicon (μc-Si) layer, wherein the first undoped μc-Si layer is disposed on the undoped amorphous silicon layer. The ohmic contact layer is disposed on part of the semiconductor layer and the source and the drain are disposed on the ohmic contact layer. Therefore, the thin film transistor has better quality control and electrical characteristics. | 09-18-2008 |
20090081855 | FABRICATION METHOD OF POLYSILICON LAYER - A fabrication method of a polysilicon layer is provided. First, a substrate is provided. Then, an amorphous silicon layer is formed on the substrate. After that, a patterned photomask having a light transmitting area and a light shielding area is provided, and the amorphous silicon layer is irradiated with a light by using the patterned photomask as a mask, wherein the amorphous silicon layer corresponding to the light transmitting area is transformed into a hydrophilic amorphous silicon layer, and the amorphous silicon layer corresponding to the light shielding area remains as a hydrophobic amorphous silicon layer. Next, a hydrophilic metal catalyst is provided and disposed on the hydrophilic amorphous silicon layer. After that, an annealing process is performed to transform the hydrophilic metal catalyst into a metal catalyst layer, and the metal catalyst layer reacts with the amorphous silicon layer to form a polysilicon layer. | 03-26-2009 |
20110318895 | FABRICATION METHOD OF TRENCHED POWER MOSFET - A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench. | 12-29-2011 |
20120299091 | TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode. | 11-29-2012 |
20130056821 | TRENCHED POWER SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region. | 03-07-2013 |
20130221435 | CLOSED CELL TRENCHED POWER SEMICONDUCTOR STRUCTURE - A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave. | 08-29-2013 |