Patent application number | Description | Published |
20090051031 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure. | 02-26-2009 |
20090230526 | ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A PROTECTIVE LAYER TO ENHANCE SURFACE MOUNTING AND MANUFACTURING METHODS THEREOF - A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead. | 09-17-2009 |
20090230564 | CHIP STRUCTURE AND STACKED CHIP PACKAGE AS WELL AS METHOD FOR MANUFACTURING CHIP STRUCTURES - A chip structure according to the present invention is provided. A plurality of pedestals extends from the back surface of the chip structure. Each of the pedestals is located at a position away from the edge of the back surface for a non-zero distance so that the pedestals of an upper chip structure will not damage the bonding pads positioned on the edge of the active surface of a lower chip structure when the upper chip structure is stacked on the active surface of the lower chip structure with the pedestals. | 09-17-2009 |
20100007004 | WAFER AND SEMICONDUCTOR PACKAGE - A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad. | 01-14-2010 |
20100007009 | SEMICONDUCTOR PACKAGE AND METHOD FOR PROCESSING AND BONDING A WIRE - A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion. | 01-14-2010 |
20100007010 | SEMICONDUCTOR PACKAGE, METHOD FOR ENHANCING THE BOND OF A BONDING WIRE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE - A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire. | 01-14-2010 |
20100007011 | SEMICONDUCTOR PACKAGE AND METHOD FOR PACKAGING A SEMICONDUCTOR PACKAGE - A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad. | 01-14-2010 |
20110156243 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication. | 06-30-2011 |
20110156739 | TEST KIT FOR TESTING A CHIP SUBASSEMBLY AND A TESTING METHOD BY USING THE SAME - A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate. | 06-30-2011 |
20110227212 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a first substrate, a second substrate, two active chips, a bridge chip and a connection structure. The first substrate has a first surface facing a second surface of the second substrate. The active chips are disposed on and electrically connected to the first surface, and spaced apart from each other by an interval, wherein the active chips respectively have a first active surface. The bridge chip is mechanically and electrically connected to the second surface, and has a second active surface partially overlapped with the first active surfaces of the active chips, such that the bridge chip is used for providing a proximity communication between the active chips. The connection structure is disposed between the first surface and the second surface for combining the first substrate and the second substrate. | 09-22-2011 |
20110233749 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively. | 09-29-2011 |
20110233764 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips. | 09-29-2011 |