Patent application number | Description | Published |
20080290380 | SEMICONDUCTOR DEVICE WITH RAISED SPACERS - A semiconductor device includes a substrate and a gate formed on the substrate. A gate spacer is formed next to the gate. The gate spacer has a height greater than the height of the gate. A method of forming a semiconductor device includes providing a substrate with a gate layer. A hard mask layer is formed over the gate layer, and both layers are then etched using a pattern, forming a gate and a hard mask. A spacer layer is then deposited over the substrate, gate, and hard mask. The spacer layer is etched to form a gate spacer next to the gate. The hard mask is then removed. | 11-27-2008 |
20080290412 | SUPPRESSING SHORT CHANNEL EFFECTS - An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate. | 11-27-2008 |
20100052065 | NEW METHOD FOR MECHANICAL STRESS ENHANCEMENT IN SEMICONDUCTOR DEVICES - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region. | 03-04-2010 |
20120119298 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - A method of forming an integrated circuit includes forming a plurality of gate structures longitudinally arranged along a first direction over a substrate. A plurality of angle ion implantations are performed to the substrate. Each of the angle ion implantations has a respective implantation angle with respect to a second direction. The second direction is substantially parallel with a surface of the substrate and substantially orthogonal to the first direction. Each of the implantation angles is substantially larger than 0°. | 05-17-2012 |
20130113042 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 05-09-2013 |
20130126981 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 05-23-2013 |
20140103438 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 04-17-2014 |
20150044847 | METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit comprises forming a first doped region in a substrate using a first angle ion implantation performed on a first side of a gate structure. The gate structure has a length in a first direction and a width in a second direction. The method also comprises forming a second doped region in the substrate using a second angle ion implantation performed on a second side of the gate structure. The first angle ion implantation has a first implantation angle with respect to the second direction and the second angle ion implantation has a second implantation angle with respect to the second direction. Each of the first implantation angle and the second implantation angle is substantially larger than 0° and less than 90°. | 02-12-2015 |