Patent application number | Description | Published |
20120026444 | LIQUID CRYSTAL DISPLAY PANEL, PIXEL ARRAY SUBSTRATE AND PIXEL STRUCTURE THEREOF - A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor. | 02-02-2012 |
20140246736 | High-K Film Apparatus and Method - Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied. | 09-04-2014 |
20160005832 | High-K Film Apparatus and Method - A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate. | 01-07-2016 |
Patent application number | Description | Published |
20140174802 | LOWDIELECTRIC RESIN COMPOSITION, COPPER CLAD LAMINATE USING THE SAME, AND PRINTED CIRCUIT BOARD USING THE SAME - A halogen-free resin composition includes (A) 100 parts by weight of naphthalene epoxy resin; (B) 10 to 100 parts by weight of styrene maleic anhydride copolymer; and (C) 30 to 70 parts by weight of DOPO-containing bisphenol F novolac resin. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby attain a low dielectric constant, a low dielectric dissipation factor, high heat resistance, and high flame retardation, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards. | 06-26-2014 |
20140178656 | HALOGEN-FREE RESIN COMPOSITION, COPPER CLAD LAMINATE USING THE SAME, AND PRINTED CIRCUIT BOARD USING THE SAME - A halogen-free resin composition includes (A) 100 parts by weight of epoxy resin; (B) 10 to 100 parts by weight of styrene-maleic anhydride (SMA) copolymer; and (C) 5 to 50 parts by weight of bisphenol S. The halogen-free resin composition includes specific ingredients, and is characterized by specific proportions thereof, to thereby achieve a high glass transition temperature, high heat resistance, and attractive appearance, and thus is suitable for producing a prepreg or resin film to thereby be applicable to copper clad laminates and printed circuit boards. | 06-26-2014 |
20140322541 | HALOGEN-FREE RESIN COMPOSITION, COPPER CLAD LAMINATE USING THE SAME, AND PRINTED CIRCUIT BOARD USING THE SAME - A halogen-free resin composition, a copper clad laminate using the same, and a printed circuit board using the same are introduced. The halogen-free resin composition comprising (A) 100 parts by weight of epoxy resin; (B) 3 to 15 parts by weight of diaminodiphenyl sulfone (DDS); and (C) 5 to 70 parts by weight of phenolic co-hardener. The halogen-free resin composition features specific ingredients and proportion to thereby achieve satisfactory maximum preservation period of the prepreg manufactured from the halogen-free resin composition, control the related manufacturing process better, and attain satisfactory laminate properties, such as a high degree of water resistance, a high degree of heat resistance, and satisfactory dielectric properties, and thus is suitable for producing a prepreg or a resin film to thereby be applicable to copper clad laminates and printed circuit boards. | 10-30-2014 |
Patent application number | Description | Published |
20130111108 | SOLID STATE DRIVE AND METHOD FOR CONTROLLING CACHE MEMORY THEREOF | 05-02-2013 |
20130132642 | SOLID STATE DRIVE - A solid state drive includes a flash memory, a cache memory, and a controlling unit. The solid state drive is in communication with a host. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The cache memory includes a plurality of cache units. The cache units are allocated into a plurality of groups according to operating statuses of respective cache units. The controlling unit is in communication with the host, the flash memory and the cache memory. Under control of the controlling unit, a write data from the host is temporarily stored in the cache memory so as to be written into the flash memory, or a read data from the flash memory is temporarily stored in the cache memory so as to be provided to the host. | 05-23-2013 |
20140133240 | SOLID STATE STORAGE DEVICE WITH SLEEP CONTROL CIRCUIT - A solid state storage device receives a device sleep signal and a power signal from a host. The solid state storage device includes a control chip, a sleep control circuit, and a regulator. If the device sleep signal is activated, the control chip temporarily stores a system parameter into a flash memory module and then generates an acknowledge signal. The sleep control circuit receives the power signal, the device sleep signal and the acknowledge signal. If both of the device sleep signal and the acknowledge signal are activated, the sleep control circuit generates a disable state and a wake-up state. Moreover, if the power signal is received by the regulator and the sleep control circuit generates the disable state, the regulator stops providing a supply voltage to the control chip, so that the solid state storage device enters a sleep mode. | 05-15-2014 |
20150186052 | STORAGE DEVICE AND DATA TRANSMISSION CONTROL METHOD THEREOF - A data transmission control method for a storage device is provided. The storage device is in communication with a host through a SATA bus. The data transmission control method includes the following steps. Firstly, a X_RDY primitive is issued from the storage device to the host. After a R_RDY primitive from the host is received by the from the storage device, a first frame is transmitted to the host. After the first frame is completely transmitted and in a specified time period before a second frame is transmitted, plural SYNC primitives are issued from the storage device to the host. If the host does not issue the X_RDY primitive in the specified time period, the second frame is transmitted to the host. | 07-02-2015 |
Patent application number | Description | Published |
20110304805 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area. | 12-15-2011 |
20120038601 | METHOD OF REPAIRING PIXEL STRUCTURE, REPAIRED PIXEL STRUCTURE AND PIXEL ARRAY - A method of repairing a pixel structure is provided. In the method, the pixel structure on a substrate is provided and includes a scan line, a data line, an active device, an insulating layer, and a pixel electrode. The scan line and the data line are located on the substrate. The active device is located on the substrate and electrically connected to the scan line and the data line. The insulating layer covers the scan line, the data line, and the active device and has a contact opening. The pixel electrode is located on the insulating layer and fills the contact opening to electrically connect the active device. A laser removing process is performed to remove the pixel electrode in the contact opening, such that the pixel electrode is electrically insulated from the active device. | 02-16-2012 |
20120138963 | PIXEL STRUCTURE - A pixel structure includes a substrate, a scan line, a first data line, a second data line, a first active device, a second active device, a first pixel electrode, and a second pixel electrode. The substrate has a first unit area and a second unit area. The first pixel electrode is disposed in the first unit area and includes a first main portion and first branch portions extending from the first main portion to an edge of the first unit area. The second pixel electrode is disposed in the second unit area and includes a second main portion and second branch portions extending from the second main portion to an edge of the second unit area, wherein at least a part of the first branch portions and at least a part of the second branch portions are asymmetrically arranged at two sides of the second data line. | 06-07-2012 |
20140071385 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel includes an active device array substrate, an opposite substrate, a sealant, a liquid crystal layer, a black matrix, and a plurality of rough structures. The active device array substrate has a display area and a peripheral area surrounding the display area, and the liquid crystal layer and the peripheral area are surrounded by the sealant. The black matrix is disposed between the active device array substrate and the opposite substrate and distributed corresponding to the display area and the peripheral area. The rough structures are disposed on a portion of the black matrix and distributed corresponding to the peripheral area. Surface roughness of the rough structures is greater than surface roughness of the black matrix distributed corresponding to the display area. | 03-13-2014 |
Patent application number | Description | Published |
20110193219 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ASSEMBLY WITH LEAD-FREE SOLDER - A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent. | 08-11-2011 |
20110309854 | Probe Card for Simultaneously Testing Multiple Dies - In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure. | 12-22-2011 |
20120056328 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 03-08-2012 |
20120217628 | METAL BUMPS FOR COOLING DEVICE CONNECTION - The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps. | 08-30-2012 |
20130026623 | Semiconductor Devices, Packaging Methods and Structures - Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region. | 01-31-2013 |
20130328215 | Die Edge Contacts for Semiconductor Devices - A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like. | 12-12-2013 |
20130328586 | Probe Card for Simultaneously Testing Multiple Dies - In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure. | 12-12-2013 |
20140070409 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR ASSEMBLY WITH LEAD-FREE SOLDER - A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag. | 03-13-2014 |
20150125998 | METAL BUMPS FOR COOLING DEVICE CONNECTION - A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps. | 05-07-2015 |
Patent application number | Description | Published |
20100092993 | QUANTITATIVE ANALYZING METHOD - This invention discloses an analyzing method for detecting a specific analyte in a fluid sample. The method comprises the following steps. First, a substrate is provided. The substrate has a channel provided concavely on an upper surface thereof. The channel comprises a first area, a second area and a third area, and these three areas are connected sequentially. Each of the second and the third areas comprises a nitrocellulose layers containing a reaction material and formed at the bottom thereof. The nitrocellulose layer of the third area can absorb a fixed volume of the fluid sample. Second, the fluid sample is applied to the first area and delivered by the second area and then to the third area. Finally, the reaction material reacts with the specific analyte in the fluid sample to produce a signal for detection. | 04-15-2010 |
20100099114 | ANALYTICAL STRIP AND DETECTING METHOD USING THE SAME - An analytical strip and a detecting method using the analytical strip are provided. The analytical strip includes a substrate having a channel thereon. The channel has a first region, a second region and a third region, which are arranged successively. A first antibody is localized in the first region. A saccharide and a peroxidase are localized in the first or second region. A second antibody for recognizing a different epitope of an identical antigen with the first antibody is immobilized in the second region. A substrate reagent including a saccharide oxidase is localized in the third region. | 04-22-2010 |
20100255512 | ANALYTICAL STRIP AND DETECTING METHOD USING THE SAME - An analytical strip and a detecting method using the analytical strip are provided. The analytical strip includes a substrate having a channel thereon. The channel has a first region, a second region and a third region, which are connected sequentially. A first antibody is localized in the first region. A saccharide and a peroxidase are localized in the first or second region. A second antibody for recognizing a different epitope of an identical antigen with the first antibody is immobilized in the second region. An optical substrate and a substrate reagent including a saccharide oxidase are localized in the third region. | 10-07-2010 |
20100285991 | COMBINATORY ANALYTICAL STRIP - A combinatory analytical strip including a substrate is disclosed. A first channel for a biochemical assay and a second channel for an immunological assay are provided concavely on an upper surface of the substrate. The results of both assays are detected by a sensor. Each channel includes a first area for receiving a fluid sample, a second area for delivering the fluid sample and a third area where the fluid sample reacts. These three areas are connected successively. A nitrocellulose layer having a hollow-matrix conformation is formed at a bottom of each of the second and third areas of both channels. Each of the nitrocellulose layers of the second areas comprises an average thickness that is not greater than that of each the nitrocellulose layers of the third areas. A reaction material is formed in the hollow-matrix conformation. The third areas of the first and second channels are both located on a line conforming a relative motion path of the sensor and the combinatory analytical strip. | 11-11-2010 |
20110243811 | SUBSTRATE OF ANALYTICAL STRIP - This invention discloses a substrate of an analytical strip. The substrate has a channel provided concavely on an upper surface of the substrate. The channel comprises a first area for receiving a fluid sample, a second area for delivering the fluid sample, and a third area where the fluid sample reacts. These areas are connected sequentially. Nitrocellulose layers are formed at bottoms of both the second area and the third area. The conformation of the nitrocellulose layers is a hollow matrix. In addition, the nitrocellulose layer of the second area has an average thickness that is not greater than that of the nitrocellulose layer of the third area. | 10-06-2011 |