Yi-Fong
Yi-Fong Chang, Dali City TW
Patent application number | Description | Published |
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20110233672 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region. | 09-29-2011 |
Yi-Fong Lin, New Taipei City TW
Patent application number | Description | Published |
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20130258743 | MEMORY ARRAY WITH HIERARCHICAL BIT LINE STRUCTURE - A memory array includes a plurality of word lines extending along a first direction; a plurality of memory cells coupled to a first sub-bit line (SBL) extending along a second direction that is substantially orthogonal to the first direction; a first selector region disposed substantially in the middle of the first SBL thereby dividing the plurality of memory cells into two sub-groups, wherein the first selector region comprises at least one selector transistor that is coupled to the first SBL; and a main bit line (MBL) extending along the second direction and coupled to the selector transistor. | 10-03-2013 |
20140041900 | Circuit Pattern with high aspect ratio and Method of Manufacturing the Same - A method of manufacturing a circuit pattern with high aspect ratio is disclosed. A plurality of parallel lines and supporting lines intersecting the parallel lines are formed. Supporting isolation structures are then formed in the space between the parallel lines and the supporting line for supporting the parallel lines in a later etching process. The parallel lines and the supporting line are then disconnected after the etching process. | 02-13-2014 |
20140252459 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. | 09-11-2014 |
Yi-Fong Wang, Taipei City TW
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20090066436 | MULTI-BRAND ELECTRONIC APPARATUS AND MULTI-BAND SIGNAL PROCESSING METHOD - A multi-band electronic apparatus and method thereof is provided. The method comprises outputting a first output signal in the first band by a first voltage controlled oscillator according to a switch control signal and a control voltage, outputting a second output signal in the second band by a second voltage controlled oscillator according to the switch control signal and the control voltage, the second band being not completely overlapped by the first band, performing frequency division selectively on the first output signal or the second frequency divided signal according to the switch control signal, and outputting a first frequency divided signal, determining a phase difference between the first frequency divided signal and a reference signal to output a phase difference signal, outputting the control voltage according to the phase difference signal, and selectively driving the first or the second voltage controlled oscillators by the control voltage according to the switch control signal. | 03-12-2009 |
Yi-Fong Wang, Taoyuan County TW
Patent application number | Description | Published |
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20120249256 | CALIBRATION CIRCUIT OF A FREQUENCY GENERATOR, frequency generator, AND COMPENSATION CIRCUIT THEREOF - A calibration circuit includes at least two compensation circuits and a comparator. The at least two compensation circuits are coupled to an input signal for outputting at least a first compensation signal and a second compensation signal respectively. The comparator is coupled to the first compensation signal and the second compensation signal for outputting a calibration signal, where the calibration signal is used for determining an oscillation frequency of a crystal oscillator to achieve a purpose of frequency compensation with a temperature. | 10-04-2012 |