Patent application number | Description | Published |
20090016406 | NOVEL METHOD FOR MONITORING AND CALIBRATING TEMPERATURE IN SEMICONDUCTOR PROCESSING CHAMBERS - The present invention provides a non-destructive method for monitoring and calibrating chamber temperature. One embodiment of the present invention provides a method for measuring temperature comprising forming a target film on a test substrate at a first temperature, wherein the target film has one or more properties responsive to thermal exposure, exposing the target film to an environment at a second temperature in a range higher than the first temperature, measuring the one or more properties of the target film after exposing the target film to the environment at the second temperature, and determining the second temperature according to the measured one or more properties. | 01-15-2009 |
20090017637 | METHOD AND APPARATUS FOR BATCH PROCESSING IN A VERTICAL REACTOR - The present invention generally provides an apparatus and method for the processing a plurality of substrates in a batch processing chamber. One embodiment of the present invention provides a method for processing a plurality of substrates comprising positioning the plurality of substrates in an inner volume of a batch processing chamber, wherein the plurality of substrates are arranged in a substantially parallel manner, and at least a portion of the plurality of substrates are positioned with a device side facing downward, and flowing one or more processing gases cross the plurality of substrates. | 01-15-2009 |
20090078198 | CHAMBER COMPONENTS WITH INCREASED PYROMETRY VISIBILITY - The present invention generally provides method and apparatus for non-contact temperature measurement in a semiconductor processing chamber. Particularly, the present invention provides methods and apparatus for non-contact temperature measurement for temperature below 500° C. One embodiment of the present invention provides an apparatus for processing semiconductor substrates. The apparatus comprises a target component comprises a material with higher emissivity than the one or more substrates. | 03-26-2009 |
20090242957 | ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer. | 10-01-2009 |
20100075488 | CVD REACTOR WITH MULTIPLE PROCESSING LEVELS AND DUAL-AXIS MOTORIZED LIFT MECHANISM - An apparatus for processing a substrate, comprising a processing chamber and a substrate support and lift pin assembly disposed within the chamber. The substrate support and lift pin assembly are coupled to a lift mechanism that controls positioning of the substrate support and the lift pins and provides rotation for the substrate support. The lift mechanism includes at least one sensor capable of generating a signal when clearance between the substrate support and the lift pins allows rotation of the substrate support to begin. The substrate support capable of concurrent axial motion and rotation may be used in a processing chamber comprising multiple processing zones separated by edge rings. Substrates may be subjected to successive or cyclical processes by moving between the multiple processing zones. | 03-25-2010 |
20100102376 | Atomic Layer Deposition Processes for Non-Volatile Memory Devices - Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate. | 04-29-2010 |
20100120235 | METHODS FOR FORMING SILICON GERMANIUM LAYERS - Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method includes depositing a silicon germanium seed layer atop the substrate using a first precursor comprising silicon and chlorine; and depositing a silicon germanium bulk layer atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H | 05-13-2010 |
20100227061 | LOW TEMPERATURE ALD Si02 - The present invention generally comprises a silicon dioxide atomic layer deposition method. By providing pyridine as a catalyst, water may be utilized as the oxidization source while depositing at a low temperature. Prior to exposing the substrate to the water, the substrate may be exposed to a pyridine soak process. Additionally, the water may be co-flowed to the chamber with the pyridine through separate conduits to reduce interaction prior to entering the chamber. Alternatively, the pyridine may be co-flowed with a silicon precursor that does not react with pyridine. | 09-09-2010 |
20100317177 | METHODS FOR FORMING SILICON GERMANIUM LAYERS - Embodiments of methods for depositing silicon germanium (SiGe) layers on a substrate are disclosed herein. In some embodiments, the method may include depositing a first layer comprising silicon and germanium (e.g., a seed layer) atop the substrate using a first precursor comprising silicon and chlorine; and depositing a second layer comprising silicon and germanium (e.g., a bulk layer) atop the silicon germanium seed layer using a second precursor comprising silicon and hydrogen. In some embodiments, the first silicon precursor gas may comprise at least one of dichlorosilane (H | 12-16-2010 |
20110306186 | METHODS FOR LOW TEMPERATURE CONDITIONING OF PROCESS CHAMBERS - Methods for removing residue from interior surfaces of process chambers are provided herein. In some embodiments, a method of conditioning interior surfaces of a process chamber may include maintaining a process chamber at a first pressure and at a first temperature of less than about 800 degrees Celsius; providing a process gas to the process chamber at the first pressure and the first temperature, wherein the process gas comprises chlorine and nitrogen to remove residue disposed on interior surfaces of the process chamber; and increasing the pressure in the process chamber from the first pressure to a second pressure while continuing to provide the process gas to the process chamber. | 12-15-2011 |
20120077335 | METHODS FOR DEPOSITING GERMANIUM-CONTAINING LAYERS - Methods for depositing germanium-containing layers on silicon-containing layers are provided herein. In some embodiments, a method may include depositing a first layer atop an upper surface of the silicon-containing layer, wherein the first layer comprises predominantly germanium (Ge) and further comprises a lattice adjustment element having a concentration selected to enhance electrical activity of dopant elements, wherein the dopant elements are disposed in at least one of the first layer or in an optional second layer deposited atop of the first layer, wherein the optional second layer, if present, comprises predominantly germanium (Ge). In some embodiments, the second layer is deposited atop the first layer. In some embodiments, the second layer comprises germanium (Ge) and dopant elements. | 03-29-2012 |
20120306054 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 12-06-2012 |
20120306055 | METHOD OF FORMING HIGH GROWTH RATE, LOW RESISTIVITY GERMANIUM FILM ON SILICON SUBSTRATE - A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium. | 12-06-2012 |
20130026540 | METHODS AND APPARATUS FOR FORMING SEMICONDUCTOR STRUCTURES - Methods and apparatus for forming semiconductor structures are disclosed herein. In some embodiments, a semiconductor structure may include a first germanium carbon layer having a first side and an opposing second side; a germanium-containing layer directly contacting the first side of the first germanium carbon layer; and a first silicon layer directly contacting the opposing second side of the first germanium carbon layer. In some embodiments, a method of forming a semiconductor structure may include forming a first germanium carbon layer atop a first silicon layer; and forming a germanium-containing layer atop the first germanium carbon layer. | 01-31-2013 |
20130183814 | METHOD OF DEPOSITING A SILICON GERMANIUM TIN LAYER ON A SUBSTRATE - Methods of depositing silicon germanium tin (SiGeSn) layer on a substrate are disclosed herein. In some embodiments, a method may include co-flowing a silicon source, a germanium source, and a tin source comprising a tin halide to a process chamber at a temperature of about 450 degrees Celsius or below and a pressure of about 100 Torr or below to deposit the SiGeSn layer on a first surface of the substrate. In some embodiments, the tin halide comprises tin tetrachloride (SnCl | 07-18-2013 |
20130183815 | METHODS FOR DEPOSITING GROUP III-V LAYERS ON SUBSTRATES - Methods for depositing a group III-V layer on a substrate are disclosed herein. In some embodiments a method includes depositing a first layer comprising at least one of a first Group III element or a first Group V element on a silicon-containing surface oriented in a <111> direction at a first temperature ranging from about 300 to about 400 degrees Celsius; and depositing a second layer comprising second Group III element and a second Group V element atop the first layer at a second temperature ranging from about 300 to about 600 degrees Celsius. | 07-18-2013 |
20130210221 | SELECTIVE EPITAXIAL GERMANIUM GROWTH ON SILICON-TRENCH FILL AND IN SITU DOPING - Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed. | 08-15-2013 |
20130240478 | METHODS FOR DEPOSITING A TiN-CONTAINING LAYER ON A SUBSTRATE - Methods of depositing a tin-containing layer on a substrate are disclosed herein. In some embodiments, a method of depositing a tin-containing layer on a substrate may include flowing a tin source comprising a tin halide into a reaction volume; flowing a hydrogen plasma into the reaction volume; forming one or more tin hydrides within the reaction volume from the tin source and the hydrogen plasma; and depositing the tin-containing layer on a first surface of the substrate using the one or more tin hydrides. | 09-19-2013 |
20130256838 | METHOD OF EPITAXIAL DOPED GERMANIUM TIN ALLOY FORMATION - A method for forming germanium tin layers and the resulting embodiments are described. A germanium precursor and a tin precursor are provided to a chamber, and an epitaxial layer of germanium tin is formed on the substrate. The germanium tin layer is selectively deposited on the semiconductor regions of the substrate and can include thickness regions of varying tin and dopant concentrations. The germanium tin layer can be selectively deposited by either alternating or concurrent flow of a halide gas to etch the surface of the substrate. | 10-03-2013 |
20130280891 | METHOD AND APPARATUS FOR GERMANIUM TIN ALLOY FORMATION BY THERMAL CVD - A method and apparatus for forming semiconductive semiconductor-metal alloy layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy, optionally including silicon, is formed on the substrate. The metal precursor is typically a metal halide, which may be provided by evaporating a liquid metal halide, subliming a solid metal halide, or by contacting a pure metal with a halogen gas. A group IV halide deposition control agent is used to provide selective deposition on semiconductive regions of the substrate relative to dielectric regions. The semiconductive semiconductor-metal alloy layers may be doped, for example with boron, phosphorus, and/or arsenic. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components. | 10-24-2013 |
20130288480 | METHOD OF EPITAXIAL GERMANIUM TIN ALLOY SURFACE PREPARATION - Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas. | 10-31-2013 |
20130295752 | METHODS FOR CHEMICAL MECHANICAL PLANARIZATION OF PATTERNED WAFERS - Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level. | 11-07-2013 |
20130330911 | METHOD OF SEMICONDUCTOR FILM STABILIZATION - Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed. | 12-12-2013 |
20140154875 | METHOD OF EPITAXIAL GERMANIUM TIN ALLOY SURFACE PREPARATION - Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of Ge, doped Ge, another GeSn or SiGeSn layer, a doped GeSn or SiGeSn layer, an insulator, or a metal can be deposited on a prepared GeSn or SiGeSn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface. Methods can also include the placement and etching of a sacrificial layer, a thermal clean using rapid thermal annealing, or a process in a plasma of nitrogen trifluoride and ammonia gas. | 06-05-2014 |
20140342533 | METHOD OF STRAIN AND DEFECT CONTROL IN THIN SEMICONDUCTOR FILMS - A method of managing strain and preventing defect formation in semiconductor materials is described. In structures featuring two or more semiconductor materials with different lattice constants, buffer layers may be used to form deposition surfaces that result in defect-free semiconductor devices. The buffer layers typically have compositions, and lattice constants, intermediate between the two semiconductor materials. The buffer layers may have stepped or graded composition, and multiple buffer layers may be used. | 11-20-2014 |
20150050800 | FIN FORMATION BY EPITAXIAL DEPOSITION - Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure. | 02-19-2015 |
20150079803 | METHOD OF FORMING STRAIN-RELAXED BUFFER LAYERS - Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects. | 03-19-2015 |