Patent application number | Description | Published |
20080301507 | System and Method for Repairing a Memory - A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation. | 12-04-2008 |
20090106716 | VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTURAL PRIMITIVE VERIFICATION FOR MEMORY COMPILERS - A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler. | 04-23-2009 |
20100050135 | VARIOUS METHODS AND APPARATUSES FOR EFFECTIVE YIELD ENHANCEMENT OF GOOD CHIP DIES HAVING MEMORIES PER WAFER - A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area. | 02-25-2010 |
20110119531 | Architecture, System And Method For Compressing Repair Data In An Integrated Circuit (IC) Design - Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances. | 05-19-2011 |
20130019130 | TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITYAANM HAKHUMYAN; AramAACI YerevanAACO AMAAGP HAKHUMYAN; Aram Yerevan AMAANM Harutyunyan; GurgenAACI AbovyanAACO AMAAGP Harutyunyan; Gurgen Abovyan AMAANM Shoukourian; SamvelAACI YerevanAACO AMAAGP Shoukourian; Samvel Yerevan AMAANM Vardanian; ValeryAACI YerevanAACO AMAAGP Vardanian; Valery Yerevan AMAANM Zorian; YervantAACI Santa ClaraAAST CAAACO USAAGP Zorian; Yervant Santa Clara CA US - Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence. | 01-17-2013 |
20130019132 | DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORYAANM AMIRKHANYAN; KarenAACI YerevanAACO AMAAGP AMIRKHANYAN; Karen Yerevan AMAANM Grigoryan; HaykAACI YerevanAACO AMAAGP Grigoryan; Hayk Yerevan AMAANM Harutyunyan; GurgenAACI AbovyanAACO AMAAGP Harutyunyan; Gurgen Abovyan AMAANM Melkumyan; TatevikAACI YerevanAACO AMAAGP Melkumyan; Tatevik Yerevan AMAANM Shoukourian; SamvelAACI YerevanAACO AMAAGP Shoukourian; Samvel Yerevan AMAANM Shubat; AlexAACI Los Altos HillsAAST CAAACO USAAGP Shubat; Alex Los Altos Hills CA USAANM Vardanian; ValeryAACI YerevanAACO AMAAGP Vardanian; Valery Yerevan AMAANM Zorian; YervantAACI Santa ClaraAAST CAAACO USAAGP Zorian; Yervant Santa Clara CA US - A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory. | 01-17-2013 |
20130080847 | MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES - A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers. | 03-28-2013 |
20130145119 | Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme - A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement. | 06-06-2013 |
20130346056 | Generation of Memory Structural Model Based on Memory Layout - A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine. | 12-26-2013 |
20140380107 | TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY - An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test. | 12-25-2014 |