Patent application number | Description | Published |
20130020693 | CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost. | 01-24-2013 |
20130168784 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board. | 07-04-2013 |
20130187263 | SEMICONDUCTOR STACKED PACKAGE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided. | 07-25-2013 |
Patent application number | Description | Published |
20100164844 | PIXEL ARRAY LAYOUT - A pixel array layout includes a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, a plurality of pixel units disposed on the substrate, and a pre-discharge conductive layer. Each of the pixel units is electrically connected to at least one of the scan lines and one of the data lines correspondingly, and each of the pixel units has a driving circuit and a pixel electrode electrically connected to the driving circuit. The pre-discharge conductive layer is electrically connected to the driving circuit and extends to an area between two adjacent pixel electrodes from an edge of the substrate, and the pre-discharge conductive layer and the pixel electrodes do not overlap. | 07-01-2010 |
20100164931 | PIXEL CIRCUIT AND METHOD FOR DRIVING A PIXEL - A pixel circuit adaptable for a pixel array including a first scan line and a second scan line is provided. An illumination unit is coupled to a first node, including a light emitting diode that illuminates based on a voltage level of the first node. A first circuit is coupled to the first node, the first scan line and a data signal. A second circuit including one or more transistors, is coupled to the first node, the second scan line and a reference voltage. The second scan line has a scan order before that of the first scan line by one or more lines. When the first scan line is activated, the first circuit passes the data signal to the first node. When the second scan line is activated, the second circuit passes the reference voltage to the first node. | 07-01-2010 |
20110096061 | DRIVING METHOD AND PIXEL DRIVING CIRCUIT FOR LED DISPLAY PANEL - A driving method for a LED display panel time-anneals threshold voltage shifting of a driving transistor. The driving transistor has a gate terminal coupled to a data input terminal, a source terminal coupled to a cathode via a LED, and a drain terminal coupled to a system voltage. The method includes inserting a black image after an image frame is displayed. During the time period of inserting the black image, a positive voltage is applied to the cathode to turn off the LED. A negative bias from the gate terminal to the drain terminal is produced to cause voltage level of the gate terminal to be less than the source terminal. | 04-28-2011 |
20110115769 | HYBRID IMAGE DISPLAY SYSTEMS AND OPERATING METHODS THREROF - A hybrid image display system and an operating method thereof. The system has an electro-phoretic display (EPD) element, an organic light emitting diode (OLED), a current generating circuit and a switch. The EPD element has a first and a second terminal. The OLED has an anode and a cathode. The current generating circuit has a power terminal, a control terminal and an output terminal, wherein the output terminal is coupled to the anode of the OLED. The switch is controlled by a scan signal. When the switch is turned on, a data signal is transmitted to the first terminal of the EPD element and to the control terminal of the current generating circuit. | 05-19-2011 |
20110254061 | TRANSISTOR AND METHOD OF FABRICATING THE SAME - A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure. | 10-20-2011 |
20110285610 | PIXEL STRUCTURE AND PIXEL CIRCUIT HAVING MULTI-DISPLAY MEDIUMS - A pixel structure and a pixel circuit having multi-display mediums are provided. A storage capacitor and a first display medium are disposed in different layers, so as to overlap the storage capacitor with a pixel electrode of the first display medium. Accordingly, an area of the first display medium can be increased for enlarging an aperture ratio of the pixel. Furthermore, because a third pixel electrode is disposed in a conductive layer, the third pixel electrode can control/drive a second display medium under a substrate. | 11-24-2011 |
20120061689 | LIGHT-EMITTING DEVICE AND METHOD MANUFACTURING THE SAME - A light-emitting device and a method for manufacturing the same are provided. The light-emitting device comprises a substrate, a light-emitting element and a light-electricity-transforming element. The substrate has a first region and a second region which are non-overlapping. The light-emitting element is disposed over the substrate and located in the second region. The light-electricity-transforming element is disposed over the substrate and located in the first region. At least a portion of a side wall of the light-electricity-transforming element corresponds to at least a portion of a side wall of the light-emitting element, so that at least a side light from the light-emitting element is received and transformed into an electricity power by the light-electricity-transforming device. | 03-15-2012 |