Patent application number | Description | Published |
20100019826 | SWITCHED CAPACITOR CIRCUIT CAPABLE OF MINIMIZING CLOCK FEEDTHROUGH EFFECT AND HAVING LOW PHASE NOISE AND METHOD THEREOF - A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge circuit coupled to the first positive side node for precharging the first positive side node to a precharge voltage for a predetermined time when the first positive side switch element is switched off according to the first control signal, and then for charging the first positive side node to a charge voltage until the first positive side switch element is switched on according to the first control signal. By rapidly precharging the first positive side node, the clock feedthrough effect is eliminated and the locking period of the VCO is shortened. Afterwards by charging the first positive side node, the phase noise of the VCO is minimized. | 01-28-2010 |
20140168014 | Antenna Apparatus and Method - An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer. | 06-19-2014 |
20140185264 | METHODS AND APPARATUS FOR FORMING PACKAGE-ON-PACKAGES - Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors. | 07-03-2014 |
20150042438 | TUNABLE THREE DIMENSIONAL INDUCTOR - A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process. | 02-12-2015 |
Patent application number | Description | Published |
20080237792 | SEMICONDUCTOR CAPACITOR STRUCTURE AND LAYOUT PATTERN THEREOF - The present invention provides a metal-oxide-metal (MOM) capacitor structure having a plurality of symmetrical ring type sections. The MOM capacitor structure of the present invention does not need photomasks above standard CMOS process, and thus the process cost is cheaper. In addition, due to the semiconductor process improvement, a significantly large number of metal layers can be stacked in the MOM capacitor structure, and since the distance between the metal layers becomes smaller, the unit capacitance will be increased. | 10-02-2008 |
20080251841 | MOS TRANSISTOR AND MANUFACTURING METHOD THEREOF - The structure of the MOS transistor provided in this invention has LDD (lightly doped drain) and halo doped regions removed from the source, the drain or both regions in the substrate for improved linearity range when operated as a voltage-controlled resistor. The removal of the LDD and halo doped regions is performed by simply modifying the standard mask of the MOS process using a logic operation layer with no extra mask required. | 10-16-2008 |
20090091875 | SEMICONDUCTOR CAPACITOR STRUCTURE AND LAYOUT PATTERN THEREOF - The present invention provides a metal-oxide-metal (MOM) capacitor structure composed of a first capacitor and a second capacitor. The MOM capacitor structure has a plurality of symmetrical branch sections, which form an interdigitated structure along a plurality of ring contours. The MOM capacitor structure has an optimal geometrical symmetry, and therefore a better capacitance matching effect can be obtained, and the MOM capacitor structure has a higher unit capacitance. In addition, a capacitance value ratio between the first capacitor and the second capacitor can be adjusted according to different requirements in the MOM capacitor structure. Furthermore, the MOM capacitor structure of the present invention does not need additional masks, and the process cost is cheaper. In addition, due to the semiconductor process improvement, a large amount of metal layers can be stacked, and since the distance between the metal layers becomes smaller, the unit capacitance becomes higher. | 04-09-2009 |
20090146252 | INTEGRATED INDUCTOR STRUCTURE - This invention provides an integrated inductor structure including a substrate, a metal coil layer on the substrate and a dielectric layer between the substrate and the metal coil layer. A well shielding structure for reducing eddy current is disposed in the substrate under the metal coil layer. The well shielding structure is chequered with a plurality of N wells and a plurality of P wells. The N wells and P wells are arranged in a chessboard-like manner. A P+ pickup ring is provided in the substrate to encompass the well shielding structure. A guard ring is formed directly on the P+ pickup ring. | 06-11-2009 |
20100295648 | STACKED STRUCTURE OF A SPIRAL INDUCTOR - A stacked structure of a spiral inductor includes a first metal layer, a second metal layer, a first set of vias, and a second set of vias. The first metal layer includes a first segment, a second segment, and a third segment, wherein the layout direction of the third segment is different from the layout direction of the first and second segments. The second metal layer includes a fourth segment, a fifth segment, and a sixth segment connected to the fifth segment, wherein the layout direction of the sixth segment is different from the layout direction of the fourth and fifth segments. The first set of vias connects the first and fourth segments, and they construct a first shunt winding. The second set of vias connects the second and fifth segments, and they construct a second shunt winding. The third and sixth segments construct a crossover region. | 11-25-2010 |
20120223796 | VARIABLE INDUCTOR - A variable inductor includes an inductor element and a first inductance adjusting circuit. The first inductance adjusting circuit includes a first open-loop structure and a first switch element. The first switch element is coupled to the first open-loop structure. When the first switch element is in a conducting state, the first open-loop structure and the first switch element forms a first closed-loop to induce a first magnetic flux which alters a magnetic flux from the inductor element in operation. | 09-06-2012 |