Patent application number | Description | Published |
20120212245 | CIRCUIT AND METHOD FOR TESTING INSULATING MATERIAL - An integrated circuit is disclosed. The integrated circuit includes an insulating material layer. The integrated circuit also includes a metal structure. Furthermore, the integrated circuit includes a via through the insulating material layer that is coupled to the metal structure for testing insulating material by applying dynamic voltage switching to two adjacent metal components of the metal structure. | 08-23-2012 |
20140036578 | SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT - Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node. | 02-06-2014 |
20140070364 | ANTI-FUSE DEVICE - An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate. | 03-13-2014 |
20140131799 | METHOD AND APPARATUS FOR SELECTIVELY IMPROVING INTEGRATED DEVICE PERFORMANCE - An apparatus for selectively improving integrated circuit performance is provided. In an example, an integrated circuit is fabricated according to an integrated circuit layout. A critical portion of the integrated circuit layout determines a speed of the integrated circuit, where at least a part of the critical portion includes at least one of a halo implant region, lightly doped drain (LDD) implant region, and source drain extension (SDE) implant region. A marker layer comprises the part of the critical portion that includes the at least one of the halo implant region, the lightly doped drain (LDD) implant region, and the source drain extension (SDE) implant region, and includes at least one transistor formed therefrom. | 05-15-2014 |
20140211546 | STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS - Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance. | 07-31-2014 |
20150035019 | METHOD OF FORMING FINS FROM DIFFERENT MATERIALS ON A SUBSTRATE - A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed. | 02-05-2015 |
20150035072 | METHODS AND APPARATUSES FOR FORMING MULTIPLE RADIO FREQUENCY (RF) COMPONENTS ASSOCIATED WITH DIFFERENT RF BANDS ON A CHIP - A method includes forming a first gate oxide in a first region and in a second region of a wafer. The method further includes performing first processing to form a second gate oxide in the second region. The second gate oxide has a different thickness than the first gate oxide. The method also includes forming first gate material of a first device in the first region and forming second gate material of a second device in the second region. The first device corresponds to a first radio frequency (RF) band and the second device corresponds to a second RF band that is different from the first RF band. | 02-05-2015 |
20150036417 | SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN - A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter. | 02-05-2015 |
20150076704 | REVERSE SELF ALIGNED DOUBLE PATTERNING PROCESS FOR BACK END OF LINE FABRICATION OF A SEMICONDUCTOR DEVICE - In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench. | 03-19-2015 |
20150115473 | HETEROGENEOUS CHANNEL MATERIAL INTEGRATION INTO WAFER - Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device. | 04-30-2015 |
20150145069 | SILICON GERMANIUM FINFET FORMATION - Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin. | 05-28-2015 |
20150145070 | MERGING LITHOGRAPHY PROCESSES FOR GATE PATTERNING - Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length. | 05-28-2015 |
20150155364 | THRESHOLD VOLTAGE ADJUSTMENT IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SILICON OXYNITRIDE POLYSILICON GATE STACK ON FULLY DEPLETED SILICON-ON-INSULATOR - A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively. | 06-04-2015 |
20150162404 | SYSTEM AND METHOD OF MANUFACTURING A FIN FIELD-EFFECT TRANSISTOR HAVING MULTIPLE FIN HEIGHTS - An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer. | 06-11-2015 |
20150194339 | CONDUCTIVE LAYER ROUTING - Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices. | 07-09-2015 |
20150194525 | SILICON GERMANIUM FINFET FORMATION BY GE CONDENSATION - A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film. | 07-09-2015 |
Patent application number | Description | Published |
20090288045 | Design-For-Test-Aware Hierarchical Design Planning - Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains. | 11-19-2009 |
20120198409 | Two-Chip Co-Design And Co-Optimization In Three-Dimensional Integrated Circuit Net Assignment - A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations. | 08-02-2012 |
20130036397 | Standard Cell Placement Technique For Double Patterning Technology - A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table. | 02-07-2013 |
Patent application number | Description | Published |
20110302536 | USER MOVEMENT INTERPRETATION IN COMPUTER GENERATED REALITY - Technologies are generally described for a system for interpreting user movement in computer generated reality. In some examples, the system includes a user interface effective to generate movement data relating to movement of the user interface. In some examples, the system further includes a processor receive the movement data. In some examples, the processor is further effective to define a coordinate system based on the movement data and map the movement data to the coordinate system to produce mapped movement data. In some examples, the processor is further effective to determine a feature of the mapped movement data and to map the feature to a code. In some examples, the processor is further effective to send the code to the application and receive application data from the application in response to the code. In some examples, the processor is further effective to generate an image based on the application data. | 12-08-2011 |
20130179291 | BANDWIDTH AUCTIONS - Technologies and implementations for facilitating and participating in bandwidth auctions are generally disclosed. | 07-11-2013 |
20130212442 | MONITORING CONNECTION QUALITY - In one example monitoring connection quality, data transceiving at a socket may be monitored by frequent pinging. Any error codes identified by the socket may be assigned a corresponding error description, which may then be transmitted to a proper entity for correction. | 08-15-2013 |
20130237157 | MEASURING QUALITY OF EXPERIENCE ASSOCIATED WITH A MOBILE DEVICE - Implementations and techniques for measuring quality of experience associated with a mobile device are generally disclosed. | 09-12-2013 |
20140129289 | MEASURING QUALITY OF EXPERIENCE ASSOCIATED WITH A MOBILE DEVICE - Implementations and techniques for measuring quality of experience associated with a mobile device are generally disclosed. | 05-08-2014 |
Patent application number | Description | Published |
20080203283 | OPTICAL ENCODER WITH DETECTOR LENS - An optical encoder of a transmissive optical encoding system is disclosed. The optical encoder includes an emitter, a detector, and a detector lens. The emitter includes a light source and a collimating lens. The detector includes a plurality of photosensors to detect light from the emitter. The detector lens is aligned with the plurality of photosensors to direct the light toward the plurality of photosensors. Embodiments of the optical encoder provide an increased effective sensing area, increased power delivery to the detector, and increased encoder life. | 08-28-2008 |
20100155586 | Optical Encoder Systems, Devices and Methods - Disclosed are various embodiments of high-speed, high-performance, low-noise optical encoders having various means for preventing undesired stray light from reaching light detectors incorporated therein. Structures employed to block stray light in the optical encoders include light barriers, air gap trenches, and coatings disposed between first and second sides of a substrate of the encoder. Also disclosed are compact single track optical encoders having a single dome lens disposed thereover, and dual track triple dome lens optical encoders. Methods of making such optical encoders are also disclosed. | 06-24-2010 |
20100314532 | Optical Encoder Systems, Devices and Methods - Disclosed are various embodiments of high-speed, high-performance, low-noise optical encoders having various means for preventing undesired stray light from reaching light detectors incorporated therein. Structures employed to block stray light in the optical encoders include light barriers, air gap trenches, and coatings disposed between first and second sides of a substrate of the encoder. Also disclosed are compact single track optical encoders having a single dome lens disposed thereover, and dual track triple dome lens optical encoders. Methods of making such optical encoders are also disclosed. | 12-16-2010 |
20120104242 | Optical Reflective Encoder Systems, Devices and Methods - Disclosed are various embodiments of high-speed, high-performance, low-noise, low-cost, compact, optical encoders having a multi-faceted flat-faced lens disposed over the light emitters and light detectors thereof. Disclosed also are various means for preventing undesired stray light from reaching light detectors incorporated therein. Structures employed to block stray light in the optical encoders include light barriers, air gap trenches, and coatings disposed between first and second sides of a substrate of the encoder. Methods of making such optical encoders are also disclosed. | 05-03-2012 |
20130037705 | ENHANCED OPTICAL REFLECTIVE ENCODER - An optical encoder and optical encoding system are disclosed. Specifically, an encoder having a light detector elevated relative to a light source is described. The relative height difference between the light source and the light detector enables the optical encoder to minimize noise at the light detector without requiring a separate light baffle between the light source and light detector. Methods of manufacturing and operating such an encoder are also described. | 02-14-2013 |