Patent application number | Description | Published |
20080290403 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer. | 11-27-2008 |
20110018055 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion. | 01-27-2011 |
20110233656 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region. | 09-29-2011 |
20110291181 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately. | 12-01-2011 |
20120061721 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer. | 03-15-2012 |
20120074491 | POWER SEMICONDUCTOR DEVICE - In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other. | 03-29-2012 |
20120241823 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode. | 09-27-2012 |
20130069158 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar. | 03-21-2013 |
20130093003 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same. | 04-18-2013 |
Patent application number | Description | Published |
20080315297 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ⅕ the carrier lifetime in the drift layer in the device region. | 12-25-2008 |
20090101974 | SEMICONDUCTOR DEVICE - A semiconductor device includes an n+ type semiconductor substrate | 04-23-2009 |
20090236697 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part. | 09-24-2009 |
20100038712 | POWER SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=N | 02-18-2010 |
Patent application number | Description | Published |
20130277763 | POWER SEMICONDUCTOR DEVICE - In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other. | 10-24-2013 |
20140117445 | POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer. | 05-01-2014 |