# Yasuo Hidaka, Cupertino US

## Yasuo Hidaka, Cupertino, CA US

Patent application number | Description | Published |
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20090086809 | Method and System for On-Line Data-Pattern Compensated Adaptive Equalizer Control - In accordance with a particular embodiment of the present invention, a method is offered that includes providing a filter and an adaptive control element that is operable to communicate with the filter. The method also includes measuring, over a period, a data correlation matrix and an uncompensated error correlation vector using first and second low pass filters. In addition, the method includes implementing a data-pattern compensation matrix online, whereby the data-pattern compensation matrix is obtained online dynamically from the data correlation matrix. | 04-02-2009 |

20090086810 | Method and System for Static Data-Pattern Compensated Adaptive Equalizer Control - In accordance with a particular embodiment of the present invention, a method is offered that includes characterizing a data correlation matrix for an idle pattern offline in a filter environment and, further, using a static adaptive control scheme with a static value of a data-pattern compensation matrix to achieve a compensated adaptive equalizer control. In more specific embodiments, the adaptive control scheme is used with a ZF adaptation scheme in conjunction with a constant adaptation matrix. In other embodiments, the adaptive control scheme is used with a fast steepest-descent method using a variable adaptation matrix. In still other embodiments, the adaptive control scheme is used with a constant adaptation matrix, whereby a value of is statically calculated. If the adaptive control scheme is used with a decoupling matrix, a value of is statically calculated. An inverter is used between the data correlation matrix and the data-pattern compensation matrix. | 04-02-2009 |

20090086989 | Method and System for Providing Fast and Accurate Adaptive Control Methods - In accordance with a particular embodiment of the present invention, a method is offered that includes providing a low-pass filter in an adaptive filter architecture employing a fast steepest descent method. The method further includes decomposing an error signal, injecting a small change to one or more weight parameters for a linear combiner, measuring changes in an error correlation vector, and calculating one or more gradients, wherein the gradients are processed by the low-pass filter. In more particular embodiments, one or more of the gradients are processed by the low-pass-filter in order to remove measurement noise and improve accuracy. In addition, a real gradient of the error correlation vector is monitored such that adaptations can be made due to non-linearity and non-constant characteristics of a channel. The low-pass filter may be replaced with a Kalman Filter for faster convergence. | 04-02-2009 |

20090315592 | PREEMPHASIS DRIVER WITH REPLICA BIAS - In one embodiment, a system includes a replica driver that includes n-type digital-to-analog converter (NDAC) current sources. The replica driver can produce a reference voltage based on current supplied by the NDAC current sources. The system includes driver fingers that are coupled to the replica driver and each include a driver bias circuit and an output driver. The driver bias circuit includes an operational amplifier (op-amp) that can adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver. | 12-24-2009 |

20090316767 | Detecting Residual ISI Components Using Two Data Patterns - In one embodiment, a method includes accessing an input signal from a receiver that includes a series of bits and further comprising residual boundary intersymbol interference (ISI). The method includes identifying a first bit sequence in the input signal and identifying a second bit sequence in the input signal that differs from the first bit sequence with respect to one or more data values of one or more bits in the first and second bit sequences corresponding to particular residual boundary ISI for measurement. The method includes determining a difference between first boundary error in the first bit sequence and second boundary error in the second bit sequence and measuring the particular residual boundary ISI by the difference for use in adaptive equalizer control. | 12-24-2009 |

20090316769 | DECISION FEEDBACK EQUALIZER (DFE) - In one embodiment, a method includes receiving an input signal from a receiver, receiving a data clock (DCLK) signal, and receiving a boundary clock (BCLK) signal. The method includes, based on the input signal and the DCLK signal, recovering data from the input signal to produce a first output signal. The method includes, based on the input signal and the BCLK signal, recovering boundaries between bits in the input signal to produce a second output signal. The method includes, based on the first and second output signals, producing the DCLK and BCLK signals, with the DCLK signal being delayed with respect to the BCLK signal less than approximately 0.5 unit intervals (UIs) and greater than or equal to approximately zero UIs. | 12-24-2009 |

20090316770 | ADAPTIVE CONTROL OF A DECISION FEEDBACK EQUALIZER (DFE) - In one embodiment, a system includes one or more DFEs, each of which includes a feedback (FB) loop to compensate for distortion in an output signal that includes information recovered by a decision circuit from an input signal from a receiver. A first FB tap of a data DFE delays a first output signal of a first decision circuit by approximately 1.0 UIs and multiplies the 1.0-UI-delayed first output signal by a first data FB coefficient derived from a first boundary FB coefficient. A first FB tap of a boundary DFE delays the first output signal by approximately 1.5 UIs and multiplies the 1.5-UI-delayed first output signal by the first boundary FB coefficient, which corresponds to ISI at approximately 1.5 UIs of delay in the input signal. | 12-24-2009 |

20090316771 | Sign-Based General Zero-Forcing Adaptive Equalizer Control - In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer that produced the second output signal and the residual ISI detector that produced the first output signal, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI. | 12-24-2009 |

20090316772 | Multidimensional Asymmetric Bang-Bang Control - In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer, the residual ISI detector that, and the sign of the residual ISI, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI. | 12-24-2009 |

20120207202 | Adaptive Phase Equalizer - In particular embodiments, a method includes generating by a data detector a recovered data signal from a phase-equalized signal based on the transmitted data in the phase-equalized signal; comparing by a phase-distortion detector the phase-equalized signal and the recovered data signal with each other; based on the comparison, determining by the phase-distortion detector a phase-distortion level; generating by the phase-distortion detector a phase-distortion-level signal based on the phase-distortion level; generating by an integrator a phase-equalize-level signal based on the phase-distortion-level signal; and adjusting by a phase equalizer a transmitted-data signal based on the phase-equalize-level signal, the adjustment of the transmitted-data signal providing the phase-equalized signal or a phase pre-distorted signal configured to be distorted into the phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising the transmitted data. | 08-16-2012 |

20120207203 | Analog Continuous-Time Phase Equalizer for Data Transmission - In particular embodiments, a method includes receiving as an input signal a phase-distorted signal or a transmitted-data signal, the phase-distorted signal having been distorted from a phase-equalized signal by transmission across a communication channel, the transmitted-data signal comprising transmitted data; generating a non-derivative version of the input signal by applying a delay operator in a continuous-time domain to the input signal; generating a derivative version of the input signal by applying a derivative operator in a continuous-time domain to the input signal; generating a first product signal by multiplying the non-derivative version of the input signal by a first coefficient, the first coefficient being a positive number; generating a second product signal by multiplying the derivative version of the input signal by a second coefficient, the second coefficient being a negative number; and generating an output signal by summing the first and second product signals. | 08-16-2012 |

20120207204 | Clock Recovery Circuit for Receiver Using Decision Feedback Equalizer - In particular embodiments, a method includes receiving by a decision feedback equalizer (DFE) a first signal comprising transmitted data; adjusting by the DFE the first signal to an equalized signal comprising the transmitted data; detecting by a phase-error detector phase errors at a data rate of no more than one fourth of a data rate for the transmitted data; generating by the phase-error detector a phase-error level based on the detected phase errors; and recovering, by a clock-recovery circuit for the DFE and the phase-error detector, a clock signal associated with the transmitted data based on the phase error level. | 08-16-2012 |