Patent application number | Description | Published |
20080197932 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals. | 08-21-2008 |
20080218216 | Metastable-resistant phase comparing circuit - A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth inverters for inverting respective signals output from the first and second inverters; a delay circuit for delaying the control clock signal by a specific time; a coincidence control circuit for setting the delayed control clock signal to be active when the signals from the third and fourth inverters coincide with each other, and setting it to be inactive when the signals from the third and fourth inverters do not coincide with each other; and a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal. | 09-11-2008 |
20090016127 | DUTY DETECTION CIRCUIT, DLL CIRCUIT USING THE SAME, SEMICONDUCTOR MEMORY CIRCUIT, AND DATA PROCESSING SYSTEM - A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured. | 01-15-2009 |
20090039930 | DLL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE USING THE SAME, AND DATA PROCESSING SYSTEM - A DLL circuit includes a delay line (CDL) ( | 02-12-2009 |
20090066390 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit which receives a first clock having a period T | 03-12-2009 |
20090086551 | Semiconductor device - Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin. | 04-02-2009 |
20090102524 | TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal. | 04-23-2009 |
20090146716 | Timing control circuit, timing generation system, timing control method and semiconductor memory device - A timing control circuit DLY | 06-11-2009 |
20090289676 | DLL circuit - A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit. | 11-26-2009 |
20090289679 | Duty correction circuit - A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage. | 11-26-2009 |
20090289689 | Signal output circuit and selector circuit using the same - A signal output circuit adapted to a selector circuit is constituted of an inverter circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, and a control circuit which maintains the input terminal of the inverter circuit at a predetermined potential irrespective of the level of the input signal in the inactive level of the control signal. This achieves high-speed and high-precision propagation of the input signal. The selector circuit is formed using a plurality of signal output circuits so as to selectively output one of first and second input signals in response to the control signal. | 11-26-2009 |
20130070536 | SEMICONDUCTOR DEVICE LATCHING DATA SIGNAL IN RESPONSE TO STROBE SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal. | 03-21-2013 |
20130163353 | SEMICONDUCTOR DEVICE HAVING ODT FUNCTION - Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other. | 06-27-2013 |
20140001639 | SEMICONDUCTOR DEVICE HAVING SILICON INTERPOSER ON WHICH SEMICONDUCTOR CHIP IS MOUNTED | 01-02-2014 |