Patent application number | Description | Published |
20110081769 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A chip provided with a layer for separation of a surface region and a hydrophilic surface is manufactured. One or both of a hydrophilic region and a hydrophobic region are formed on a substrate surface where the chip is placed. Liquid is dropped onto the hydrophilic region on the substrate surface, and the chip is placed thereon. The substrate and the chip are heated while being pressure-bonded so that the chip is fixed on the substrate surface, and then the surface region of the chip is separated. By providing a liquid layer in a position where the chip is placed, the chip can be placed on the substrate with high accuracy and thus productivity can be increased. | 04-07-2011 |
20110175646 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 07-21-2011 |
20110182110 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column. | 07-28-2011 |
20110193078 | FIELD EFFECT TRANSISTOR - An object is to provide a structure with which the off-state current of a field effect transistor including a conductor-semiconductor junction can be reduced. A semiconductor layer is provided in contact with a first conductor electrode and a second conductor electrode which include a material with a work function that is at the same level as or lower than the electron affinity of the semiconductor layer. A third conductor electrode is formed using a material whose work function is higher than the electron affinity of the semiconductor layer to be in contact with a surface of the semiconductor layer opposite to a surface provided with a gate and to cross the semiconductor layer, so that a Schottky barrier junction is formed in the semiconductor layer. The carrier concentration of the portion including the Schottky barrier junction is extremely low; thus, the off-state current can be reduced. | 08-11-2011 |
20110193182 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured. | 08-11-2011 |
20110205774 | SEMICONDUCTOR MEMORY DEVICE, DRIVING METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. The other electrode of the capacitor is connected to a reading word line. In order to decrease the number of wirings, the writing bit line is substituted for the reading bit line. The reading bit line is formed so as to be embedded in a groove-like opening formed over a substrate. | 08-25-2011 |
20110216571 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. In order to reduce the number of wirings, a writing word line to which the gate of the writing transistor is not connected is substituted for the reading word line. Further, the writing bit line is substituted for the reading bit line. | 09-08-2011 |
20110228584 | SEMICONDUCTOR MEMORY DEVICE - In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared. | 09-22-2011 |
20110249484 | SEMICONDUCTOR MEMORY DEVICE - An object is to provide a semiconductor memory device which stores data with the use of a transistor having small leakage current between a source and a drain in an off state as a writing transistor. In a matrix including a plurality of memory cells, gates of the writing transistors are connected to writing word lines. In each of the memory cells, a drain of the writing transistor is connected to a gate of a reading transistor, and the drain is connected to one electrode of a capacitor. Further, the other electrode of the capacitor is connected to a reading word line. In the semiconductor memory device in which the memory cells are connected in series so as to have a NAND structure, gates of the reading transistors are provided alternately, and the reading word line and the writing word line are shared. | 10-13-2011 |
20110260158 | SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device storing data, in which a transistor whose leakage current between a source/drain in off state is small is used as a writing transistor. In a matrix of a memory unit formed of two memory cells, in each of which a drain of a writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor, a gate of the writing transistor, and the other electrode of the capacitor in a first memory cell are connected to a first word line, and a second word line, respectively. In a second memory cell, a gate of the writing transistor, and the other electrode of the capacitor are connected to the second word line, and the first word line, respectively. Further, to increase the degree of integration, gates of the reading transistors of memory cells are disposed in a staggered configuration. | 10-27-2011 |
20110279356 | ELECTRO-OPTICAL DISPLAY DEVICE AND DISPLAY METHOD THEREOF - A method of reducing power consumption of an electro-optical display device which can display a still image with the use of analog signals. A circuit in which a small amount of leakage current flows between a source and a drain of a selection transistor when the selection transistor is off; the source of the selection transistor is connected to a gate of an N-channel driving transistor, a gate of a P-channel driving transistor, and one electrode of a capacitor; and a source of each of the N-channel driving transistor and the P-channel driving transistor is connected to one electrode of a display element is provided in each pixel. The longest time of one frame is set to 100 seconds or longer with the use of such a circuit, whereby power consumption at the time of rewriting is reduced. | 11-17-2011 |
20110279419 | ELECTRO-OPTICAL DISPLAY DEVICE AND DISPLAY METHOD THEREOF - A method of reducing power consumption of an electro-optical display device which can display a still image with the use of analog signals. A circuit in which low leakage current flows between a source and a drain of a selection transistor when the selection transistor is off; the source of the selection transistor is connected to a gate of a first driving transistor, a gate of a second driving transistor, and one electrode of a display element; and a source of the second driving transistor is connected to the other electrode of the display element is provided in each pixel. A gate and the drain of the selection transistor are connected to a scan line and a signal line, respectively. A drain of the first driving transistor is connected to a first power supply line. A drain of the second driving transistor is connected to a second power supply line. | 11-17-2011 |
20110291092 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer. | 12-01-2011 |
20110309411 | FIELD EFFECT TRANSISTOR - An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a Fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor. In the first semiconductor layer, a region in the vicinity of the junction surface with the second oxide semiconductor which satisfies the above condition is a region having an extremely low carrier concentration (a quasi-i-type region). By using the region as a channel, the off-state current can be reduced. Further, a drain current of the FET flows through the first oxide semiconductor having a high mobility; accordingly, a large amount of current can be extracted. | 12-22-2011 |
20120001168 | SEMICONDUCTOR DEVICE - In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×10 | 01-05-2012 |
20120045692 | Electrical Appliance - An object is to increase the conductivity of an electrode including active material particles and the like, which is used for a battery. Two-dimensional carbon including 1 to 10 graphenes is used as a conduction auxiliary agent, instead of a conventionally used conduction auxiliary agent extending only one-dimensionally at most, such as graphite particles, acetylene black, or carbon fibers. A conduction auxiliary agent extending two-dimensionally has higher probability of being in contact with active material particles or other conduction auxiliary agents, so that the conductivity can be improved. | 02-23-2012 |
20120056175 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode ( | 03-08-2012 |
20120068183 | POWER-INSULATED-GATE FIELD-EFFECT TRANSISTOR - To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 μm to 5 μm. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode. | 03-22-2012 |
20120075917 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m | 03-29-2012 |
20120081948 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a conventional DRAM, errors in reading data are likely to occur when the capacitance of a capacitor is reduced. A plurality of cells is connected to one main bit line Each cell includes a sub bit line and 2 to 32 memory cells. Further, each cell includes a selection transistor and a reading transistor, and a sub bit line is connected to a gate of the reading transistor. Since the parasitic capacitance of the sub bit line is sufficiently small, data of electric charge of a capacitor of each memory cell can be amplified without an error in the reading transistor and output to the main bit line. | 04-05-2012 |
20120099360 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a memory cell, a transistor with extremely high off-resistance is used as a write transistor; a drain and a source of the write transistor are connected to a write bit line and an input of an inverter, respectively; and a drain and a source of a read transistor are connected to a read bit line and an output of the inverter, respectively. Capacitors may be intentionally disposed to the source of the write transistor. Alternatively, parasitic capacitance may be used. Since the data retention is performed using charge stored on these capacitors, a potential difference between power sources for the inverter can be 0. This eliminates leakage current between the positive and negative electrodes of the inverter, thereby reducing power consumption. | 04-26-2012 |
20120113707 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m. | 05-10-2012 |
20120146109 | SEMICONDUCOR DEVICE - A semiconductor device such as a transistor with an excellent OFF characteristic even when a channel is short is provided. A periphery of a source is surrounded by an extension region and a halo region, a periphery of a drain is surrounded by an extension region and a halo region, and a substrate with low impurity concentration is not in contact with the source or the drain. Moreover, a high-work-function electrode is provided via a gate insulator, and electrons entering the vicinity of a surface of the substrate from the extension regions are eliminated. With such a structure, the impurity concentration of the channel region can be decreased even when the channel is short, and a favorable transistor characteristic can be obtained. | 06-14-2012 |
20120177843 | METHOD FOR MANUFACTURING NONAQUEOUS ELECTROLYTE SECONDARY BATTERY - When an active material with low ionic conductivity and low electric conductivity is used in a nonaqueous electrolyte secondary battery such as a lithium ion battery, it is necessary to reduce the sizes of particles; however, reduction in sizes of particles leads to a decrease in electrode density. Active material particles of an oxide, which include a transition metal and have an average size of 5 nm to 50 nm, are mixed with an electrolyte, a binder, and the like to form a slurry, and the slurry is applied to a collector. Then, the collector coated with the slurry is exposed to a magnetic field. Accordingly, the active material particles aggregate so that the density thereof increases. Alternatively, the active material particles may be applied to the collector in a magnetic field. The use of the aggregating active material particles makes it possible to increase the electrode density. | 07-12-2012 |
20120181597 | SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device having a floating gate which operates with a short channel. A high-work-function compound semiconductor having a work function of greater than or equal to 5.5 eV, such as indium nitride or zinc nitride, is used for the floating gate. Accordingly, the potential barrier of the floating gate insulating film between the substrate and the floating gate is higher than that of a conventional one, so that leakage of electric charge due to a tunnel effect can be reduced even if the thickness of the floating gate insulating film is made small. Since the thickness of the floating gate insulating film can be made small, the channel can be further shortened. | 07-19-2012 |
20120182790 | SEMICONDUCTOR MEMORY DEVICE - The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material. | 07-19-2012 |
20120193697 | SEMICONDUCTOR MEMORY DEVICE - A highly integrated DRAM is provided. A circuit for driving a memory cell array is formed over a substrate, a bit line is formed thereover, and a semiconductor region, word lines, and a capacitor are formed over the bit line. Since the bit line is located below the semiconductor region, and the word lines and the capacitor are located above the semiconductor region, the degree of freedom of the arrangement of the bit line is high. When an open-bit-line DRAM is formed, an area per memory cell less than or equal to 6F | 08-02-2012 |
20120193759 | CAPACITOR AND SEMICONDUCTOR DEVICE - A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material. | 08-02-2012 |
20120195104 | SEMICONDUCTOR MEMORY DEVICE - The capacitance of a capacitor that is required in a DRAM is reduced, whereby a highly integrated DRAM is provided. In a divided bit line type DRAM, a sub bit line is formed below a word line and a bit line is formed above the word line. The parasitic capacitance of the sub bit line is reduced by employing the divided bit line method, and further, the off resistance of a cell transistor is set high according to need; thus, the capacitance can be one tenth or less of that of a conventional DRAM. Accordingly, even when a stacked capacitor is employed, the height of the capacitor can be one tenth or less of that of a conventional one, so that a bit line can be easily provided thereover. Further, by devising a structure of the cell transistor, the area per memory cell can be reduced to 4 F | 08-02-2012 |
20120199842 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F | 08-09-2012 |
20120213000 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4 F | 08-23-2012 |
20120217486 | LIGHT-EMITTING LAYER AND LIGHT-EMITTING ELEMENT - To provide a highly efficient organic light-emitting element. An extremely thin layer (a monomolecular film or the like) containing an organic light-emitting material such as an iridium complex is provided between a layer of an n-type organic material (an organic material having a high electron-transport property) and a layer of a p-type organic material (an organic material having a high hole-transport property). In a structure described above, in a layer of the organic light-emitting material, electrons are injected from the LUMO of the n-type organic material to the LUMO of the organic light-emitting material, and holes are injected from the HOMO of the p-type organic material to the HOMO of the organic light-emitting material, whereby the organic light-emitting material is brought into an excited state and emits light. | 08-30-2012 |
20120217487 | Light-Emitting Device - A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more. | 08-30-2012 |
20120241739 | FIELD-EFFECT TRANSISTOR, AND MEMORY AND SEMICONDUCTOR CIRCUIT INCLUDING THE SAME - Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to | 09-27-2012 |
20120257440 | MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - An object is to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed, and a signal processing circuit including the memory device. In a memory element including a phase-inversion element such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the above switching element, a transistor including amorphous silicon, polysilicon, microcrystalline silicon, or a compound semiconductor such as an oxide semiconductor in a channel formation region is used. The channel length of the transistor is ten times or more as large as the minimum feature size or greater than or equal to 1 μm. The above memory element is used for a memory device such as a register or a cache memory in the signal processing circuit. | 10-11-2012 |
20120262982 | MEMORY DEVICE AND DRIVING METHOD OF THE MEMORY DEVICE - A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching element is designed so that the off-state current is sufficiently low. Therefore, even when power supply of the inverter is stopped after charge corresponding to data is stored in the capacitor, data can be held for a long period of time. In order to return data, potentials of output and input terminals of the inverter are set to a precharge potential, then charge in the capacitor is released, and power is supplied to the inverter. A switching element for supplying the precharge potential may be provided. | 10-18-2012 |
20120275213 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - In a semiconductor memory device, one electrode of a capacitor is connected to a bit line, and the other electrode of the capacitor is connected to a drain of a cell transistor. A source of the cell transistor is connected to a source line. When a stack capacitor, for example, is used in this structure, one electrode of the capacitor is used as part of the bit line. An impurity region formed on the semiconductor substrate or a wiring parallel to a word line can be used as the source line; thus, the structure of a DRAM is simplified. | 11-01-2012 |
20120287700 | GAIN CELL SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten. | 11-15-2012 |
20120287701 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A memory device with low power consumption and a signal processing circuit including the memory device are provided. In a memory element including a phase-inversion element by which the phase of an input signal is inverted and the signal is output such as an inverter or a clocked inverter, a capacitor which holds data, and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For example, one of electrodes of the capacitor is connected to an input terminal or an output terminal of the phase-inversion element, and the other electrode is connected to a switching element. The above memory element is used for a memory device such as a register or a cache memory in a signal processing circuit. | 11-15-2012 |
20120293200 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation. | 11-22-2012 |
20120314482 | SEMICONDUCTOR MEMORY DEVICE - An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained. | 12-13-2012 |
20120314524 | SEMICONDUCTOR DEVICE - An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed. | 12-13-2012 |
20130003441 | SEMICONDUCTOR DEVICE AND A METHOD FOR DRIVING THE SAME - It is an object to reduce power consumption of a 2Tr1C type semiconductor memory device. The absolute value of the threshold voltage of a reading transistor is made larger than a fluctuation range of a data potential of a bit line (or the fluctuation range of the data potential of the bit line is made smaller than the absolute value of the threshold voltage of the reading transistor), whereby the potential of a source line can be fixed, a fluctuation in a potential of a writing word line can be made smaller, and a potential of a reading word line is fluctuated only at the time of reading. Further, a gate of such a transistor the absolute value of the threshold voltage of which is large is formed using a material having a high work function, such as indium nitride. | 01-03-2013 |
20130069056 | INSULATED-GATE FIELD-EFFECT TRANSISTOR - A power MISFET using an oxide semiconductor is provided. A drain electrode and a gate electrode having a trapezoidal cross section are formed with a semiconductor layer provided therebetween, a semiconductor layer is formed on a side surface of the gate electrode, and a source electrode is in contact with the semiconductor layer at a portion which overlaps with the top of the gate electrode. Between the drain electrode and the source electrode of such a power MISFET, a power source of 500 V or more and a load are connected in series, and a control signal is input to the gate electrode. Other structures and operating methods are also disclosed. | 03-21-2013 |
20130083588 | MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - In a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided. For example, one electrode of the capacitor is connected to a first node, which is an input or output terminal of one of the pair of inverters, and the other electrode of the capacitor is connected to one electrode the switching element. The other electrode of the switching element is connected to a second node, which is the output or input terminal of the one of the pair of inverters. With such a connection structure, the absolute value of the potential difference between the first node and the second node at the time of data restoring can be large enough, whereby errors at the time of data restoring can be reduced. | 04-04-2013 |
20130100723 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device in which capacitance of a capacitor is lower and integration degree is higher. A plurality of memory blocks is connected to one bit line BL_m. A memory block MB_n_m includes a sub bit line SBL_n_m, a write switch, and a plurality of memory cells. A sub bit line SBL_n+1_m adjacent to the sub bit line SBL_n_m is connected to an amplifier circuit AMP_n/n+1_m including two inverters and two selection switches. A circuit configuration of the amplifier circuit can be changed with the selection switches. The amplifier circuit is connected to the bit line BL_m through a read switch. Because of a sufficiently low capacitance of the sub bit line SBL_n_m, potential change due to electric charges of the capacitor in each memory cell can be amplified by the amplifier circuit AMP_n/n+1_m without an error, and the amplified data can be output to the bit line BL_m. | 04-25-2013 |
20130114330 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - In a conventional DRAM, a decrease in the capacitance of a capacitor causes an error in reading data. A plurality of memory blocks MB is connected to one bit line BL_m. Each memory block MB includes a sub bit line SBL, a plurality of memory cells, and a precharge transistor. The drain of a transistor of the memory cell is connected one of the bit line BL_m and the sub bit line SBL, whereas a capacitor of the memory cell is connected to the other one of the bit line BL_m and the sub bit line SBL. The capacitance of the sub bit line SBL is sufficiently low; thus, a potential change due to electric charges of the capacitor of the memory cell can be amplified by an amplifier circuit AMP without an error and the amplified signal can be output to the bit line. | 05-09-2013 |
20130141157 | SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING SIGNAL PROCESSING CIRCUIT - A memory element capable of operating at high speed and reducing power consumption and a signal processing circuit including the memory element are provided. As a writing transistor, a transistor which is formed using an oxide semiconductor and has significantly high off-state resistance is used. In a memory element in which a source of the writing transistor is connected to an input terminal of an inverter, a control terminal of a transfer gate, or the like, the threshold voltage of the writing transistor is lower than a low-level potential. The highest potential of a gate of the writing transistor can be a high-level potential. When the potential of data is the high-level potential, there is no potential difference between a channel and the gate; thus, even when the writing transistor is subsequently turned off, a potential on the source side hardly changes. | 06-06-2013 |
20130183226 | GRAPHITE OXIDE, GRAPHENE OXIDE OR GRAPHENE, ELECTRIC DEVICE USING THE SAME AND METHOD OF MANUFACTURING THE SAME, AND ELECTRODIALYSIS APPARATUS - Highly-pure graphite oxide, graphene oxide, or graphene is mass-produced. Graphite is oxidized by an oxidizer, so that a graphite oxide solution is obtained, and electrodialysis is performed on the graphite oxide solution to remove aqueous ions, whereby the purity of graphite oxide is increased. Graphene oxide manufactured using the graphite oxide is mixed with powder, and the mixture is reduced, whereby graphene exhibiting conductive properties is yielded and the powder can be bonded. Such graphene can be used instead of a conduction auxiliary agent or a binder of a variety of batteries. | 07-18-2013 |
20130194858 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column. | 08-01-2013 |
20130228776 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE - An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured. | 09-05-2013 |
20130256658 | SEMICONDUCTOR MEMORY DEVICE - In a matrix including a plurality of memory cells, each in which a drain of a writing transistor is connected to a gate of a reading transistor and the drain is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line, a source of the writing transistor and a source of the reading transistor is connected to a bit line, and a drain of the reading transistor is connected to a reading word line. A conductivity type of the writing transistor is different from a conductivity type of the reading transistor. In order to increase the integration degree, a bias line may be substituted with a reading word line in another row, or memory cells are connected in series so as to have a NAND structure, and a reading word line and a writing word line may be shared. | 10-03-2013 |
20130286757 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error. | 10-31-2013 |
20130293262 | LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE - To optimize the arrangement of configuration data stored in a configuration memory. A lookup table includes a memory configured to store configuration data, a plurality of multiplexers each configured to select one signal from a plurality of input signals in accordance with the configuration data supplied from the memory and output the one signal, and an inverter. The plurality of multiplexers are connected in a binary tree with multiple levels. The inverter is provided between one of input terminals of a multiplexer in an uppermost level and an output terminal of a multiplexer in one level lower than the uppermost level. Signal selection is performed in each of the multiplexers so that the multiplexer in the uppermost level outputs, as an output signal, one signal of all input signals of the multiplexers in a lowermost level. | 11-07-2013 |
20130293266 | METHOD OF DRIVING SEMICONDUCTOR DEVICE - A programming element including a first transistor, a second transistor, and a capacitor between a logic circuit using a semiconductor element and a power supply is provided. In the programming element, a node where a drain electrode of the first transistor, a gate electrode of the second transistor, and one of electrodes of the capacitor are electrically connected to each other is formed. A potential can be supplied to each of a source electrode of the first transistor and the other of the electrodes of the capacitor. The power supply and the logic circuit are electrically connected to each other through a source electrode and a drain electrode of the second transistor. A connection state between the power supply and the logic circuit is controlled in accordance with the state of the second transistor. | 11-07-2013 |
20130314123 | LOOKUP TABLE AND PROGRAMMABLE LOGIC DEVICE INCLUDING LOOKUP TABLE - A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of a capacitor and the input of an inverter, and a source is connected to a first wiring. The other electrode of the capacitor is connected to a second wiring. In such a memory element, the potential of the second wiring is complementary to the potential of the first wiring when writing data; accordingly, the potential of the drain of the transistor, i.e., the potential of the input of the inverter can be higher than the high potential of the inverter. Thus, shoot-through current of the inverter at this time can be significantly reduced. As a result, power consumption in a standby state can be significantly reduced. | 11-28-2013 |
20130314125 | METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included. | 11-28-2013 |
20140021980 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 01-23-2014 |
20140247254 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device having a novel data input and output panel with high definition is provided. A method for driving the semiconductor device having the novel data input and output panel with high definition is provided. The data input and output panel includes, over a substrate, proximity sensors, signal lines electrically connected to the proximity sensors, and pixels electrically connected to the signal lines. The signal lines can supply image signals to the pixels, can supply control signals to the proximity sensors, and can be supplied with sensing signals from the proximity sensors. | 09-04-2014 |
20140252346 | SEMICONDUCTOR DEVICE - It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current. | 09-11-2014 |
20140252353 | Field-Effect Transistor, and Memory and Semiconductor Circuit Including the Same - Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface and has a thickness of greater than or equal to 1 nm and less than or equal to 30 nm, a gate insulating film formed to cover the oxide semiconductor, and a strip-like gate which is formed to cover the gate insulating film and has a width of greater than or equal to 10 nm and less than or equal to 100 nm. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate, so that electrons injected from a source or a drain can be effectively removed, and most of the space between the source and the drain can be a depletion region; thus, off-state current can be reduced. | 09-11-2014 |
20140300403 | SIGNAL PROCESSING DEVICE - A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential. The second potential is higher than the third potential. The potential difference between the first potential and the third potential may be more than or equal to 3 V and less than 4 V. The level shifter includes a current control circuit which generates a second signal for operating an amplifier circuit for a certain period in accordance with the potential change of the first signal which is input to the amplifier circuit. The output of level shifter is input to a gate of an N-channel transistor whose threshold voltage is lower than 0 V. | 10-09-2014 |
20140328106 | SEMICONDUCTOR MEMORY DEVICE - The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material. | 11-06-2014 |
20140339540 | SIGNAL PROCESSING DEVICE - A plurality of writing transistors are connected in series, and a gate of a pass transistor, an input terminal of an inverter, or the like is directly or indirectly connected to each connection portion of the writing transistors. For example, a signal processing device includes first to third pass transistors, one semiconductor layer, and first to third wirings that overlap with the semiconductor layer and do not overlap with each other. Potentials of the first to third wirings can each change conductivities of at least portions of the semiconductor layer that overlap with the respective wirings. Gates of the first to third pass transistors are electrically connected to the semiconductor layer and are brought into a floating state depending on the conductivities of the portions of the semiconductor layer. Conduction between sources and drains of the pass transistors is controlled by potentials of the gates in the floating state. | 11-20-2014 |
20140340117 | SIGNAL PROCESSING DEVICE - A signal processing device is produced. The signal processing device including a first transistor with high off-state resistance, a second transistor which controls conduction between two different nodes, a capacitor which holds electric charge, and a current control element such as a transistor or a resistor. The first node to which a gate of the second transistor and a second electrode of the current control element are connected, and the second node to which one of a source and a drain of the first transistor, a first electrode of the capacitor, and a first electrode of the current control element are connected. The capacitance (including a parasitic capacitance) of the second node is greater than ten times the capacitance (including a parasitic capacitance) of the first node. The capacitance does not affect the first node; thus, a boosting effect is large and charge retention characteristics are favorable. | 11-20-2014 |
20140355333 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor device which stores data by using a transistor whose leakage current between source and drain in an off state is small as a writing transistor. In a matrix including a plurality of memory cells in which a drain of the writing transistor is connected to a gate of a reading transistor and the drain of the writing transistor is connected to one electrode of a capacitor, a gate of the writing transistor is connected to a writing word line; a source of the writing transistor is connected to a writing bit line; and a source and a drain of the reading transistor are connected to a reading bit line and a bias line. In order to reduce the number of wirings, the writing bit line or the bias line is substituted for the reading bit line in another column. | 12-04-2014 |
20140369111 | Semiconductor Memory Device And Method For Driving The Same - In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_m. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m | 12-18-2014 |
20140370184 | Electrical Appliance - An object is to increase the conductivity of an electrode including active material particles and the like, which is used for a battery. Two-dimensional carbon including 1 to 10 graphenes is used as a conduction auxiliary agent, instead of a conventionally used conduction auxiliary agent extending only one-dimensionally at most, such as graphite particles, acetylene black, or carbon fibers. A conduction auxiliary agent extending two-dimensionally has higher probability of being in contact with active material particles or other conduction auxiliary agents, so that the conductivity can be improved. | 12-18-2014 |
20150016181 | MEMORY DEVICE AND DRIVING METHOD OF THE MEMORY DEVICE - A memory device which can reduce power consumption and a driving method thereof are disclosed. In a memory element including an inverter and the like, a capacitor for holding data and a capacitor switching element for controlling store and release of charge in the capacitor are provided. The capacitor switching element is designed so that the off-state current is sufficiently low. Therefore, even when power supply of the inverter is stopped after charge corresponding to data is stored in the capacitor, data can be held for a long period of time. In order to return data, potentials of output and input terminals of the inverter are set to a precharge potential, then charge in the capacitor is released, and power is supplied to the inverter. A switching element for supplying the precharge potential may be provided. | 01-15-2015 |
20150024577 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device in which the threshold is corrected is provided. In a semiconductor device including a plurality of transistors each includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit for supplying a signal to the gate electrode and a circuit for supplying a signal to the source or drain electrode are electrically separated from each other. The process is performed in the state where the potential of the former circuit is set higher than the potential of the latter circuit. | 01-22-2015 |
20150054548 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines. | 02-26-2015 |
20150063005 | SEMICONDUCTOR MEMORY DEVICE - An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained. | 03-05-2015 |
20150069387 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits. | 03-12-2015 |
20150072471 | FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer. | 03-12-2015 |
20150078066 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m. | 03-19-2015 |