Patent application number | Description | Published |
20080251881 | SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM - A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole. | 10-16-2008 |
20080290396 | SEMICONDUCTOR MEMORY - A semiconductor memory according to an aspect of this invention comprises a semiconductor substrate which includes a memory cell array region and an interconnect line region adjoining the memory cell array region, memory cells which are provided in the memory cell array region, contact plugs which are provided in the interconnect line region, and control gate lines which are provided so as to extend from the interconnect line region to the memory cell array region and which connect the contact plugs with the memory cells, wherein the control gate lines provided in the memory cell array region include metal silicide and the control gate lines provided in the interconnect line region include no metal silicide at any part of the interconnect line region. | 11-27-2008 |
20090016108 | NONVOLATILE SEMICONDUCTOR MEMORY - A method of reading out data from nonvolatile semiconductor memory including the steps of applying a first voltage to a bit line contact; applying a second voltage to a source line contact, wherein the second voltage is substantially smaller than the first voltage; applying a third voltage gates of third and fourth select gate transistors, the third voltage configured to bring the third and fourth select gate transistors into conduction; applying a fourth voltage to gates of the plurality of memory cell transistors of a second memory cell unit, the fourth voltage configured to bring the plurality of memory cell transistors of the second memory cell unit into conduction or not, depending on the data that is stored in the memory cell unit; and applying a fifth voltage to gates of the plurality of memory cell transistors of a first memory cell unit, the fifth voltage configured to bring the plurality of memory cell transistors of the first memory cell unit into conduction; wherein the fifth voltage is bigger than the fourth voltage. | 01-15-2009 |
20090021982 | SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF - A semiconductor memory device includes a memory cell array which includes a plurality of memory cell strings each including a plurality of memory cells and a first dummy cell, which have current paths connected in series at one end and the other end thereof, a plurality of first and second select transistors, a source line, and a bit line, wherein the first dummy cell is disposed on the source line side such that one end and the other end of the current path thereof are connected between the first select transistor and the memory cell, and a threshold voltage of the first dummy cell is higher than a neutral threshold voltage. | 01-22-2009 |
20100044769 | METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas. | 02-25-2010 |
20100173471 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor. | 07-08-2010 |
20100176422 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval. | 07-15-2010 |
20100238733 | NAND FLASH MEMORY - A NAND flash memory includes a NAND string and a control circuit, wherein in a write operation, the control circuit applies a writing voltage between a control gate of a selected memory cell to be written and a semiconductor well, and after the write operation and before performing a verification read operation of verifying whether data has been written into the selected memory cell, the control circuit performs a de-trapping operation, in which a first voltage of a same potential as that of the semiconductor well or a same polarity as that of the writing voltage is applied to the control gate of the selected memory cell and in which a second voltage of a same polarity as that of the writing voltage and larger than the first voltage as an absolute value is applied to a control gate of unselected memory cells not to be written. | 09-23-2010 |
20100314677 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region. | 12-16-2010 |
20110018046 | METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas. | 01-27-2011 |
20120099374 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a substrate including device regions extending in a first direction, a memory cell array region including a plurality of memory cells disposed on the device regions, bit lines extending in the first direction, a sense amplifier circuit connected to ends of the bit lines, and bit line contacts connecting device regions to bit lines. The memory cell array region includes first to N-th regions where N is an integer of two or more, and a K-th region is located at a greater distance from the sense amplifier circuit than a (K−1)-th region, where K is an arbitrary integer of 2 to N. Contact resistance of the bit line contacts in the K-th region is lower than contact resistance of the bit line contacts in the (K−1)-th region, each device region having constant width in the memory cell array region. | 04-26-2012 |