Patent application number | Description | Published |
20110169005 | SEMICONDUCTOR DEVICE | 07-14-2011 |
20110193853 | SCANNING SIGNAL LINE DRIVE CIRCUIT, SHIFT REGISTER AND DISPLAY DEVICE - There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB. | 08-11-2011 |
20110199354 | SCANNING SIGNAL LINE DRIVE CIRCUIT, SHIFT REGISTER, AND DRIVE METHOD OF SHIFT REGISTER - There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first dock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock. | 08-18-2011 |
20110205194 | DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME - A display device of at least one embodiment of the present invention has a connection changeover circuit, including switch elements for time-division driving, formed on a liquid crystal panel, and the switch elements are paired so that two switch elements in each pair are connected in parallel to one video signal line. The paired switch elements are turned on at the same time, and immediately before one of the switch elements is turned off upon completion of a charging period for its corresponding video signal line, only the other switch element is turned off. As a result, while maintaining drive performance, it is possible to solve the impact of fieldthrough phenomenon caused by one of the switch elements, which are transistors, and also reduce parasitic capacitance formed in the other switch element, thereby suppress the impact of fieldthrough phenomenon caused by that switch element. | 08-25-2011 |
20110273223 | SIGNAL DISTRIBUTION DEVICE AND DISPLAY DEVICE - A peripheral region of a display panel includes a signal distribution device ( | 11-10-2011 |
20120121061 | SHIFT REGISTER - A shift register according to the present invention is supported on an insulating substrate and has multiple stages that sequentially shift an output signal from one stage to the next. Each of those stages has a circuit | 05-17-2012 |
20120249502 | SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME - It is an object to realize a gate driver that can cause a scanning signal to quickly fall after a charge period in each row ends. | 10-04-2012 |
20120320008 | SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - A bistable circuit includes an input terminal ( | 12-20-2012 |
20120327057 | DISPLAY DEVICE - In a display device including a monolithic gate driver, without degrading display quality, miniaturization is achieved while reducing power consumption. | 12-27-2012 |
20130009856 | SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE HAVING THE SAME - Stability of a circuit operation in a monolithic gate driver is improved. A bistable circuit is provided with a charge replenishment circuit ( | 01-10-2013 |
20130044854 | SHIFT REGISTER AND DISPLAY DEVICE - Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal. | 02-21-2013 |
20130093743 | SCANNING SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE PROVIDED WITH SAME - In a monolithic gate driver, a power consumption is reduced as compared with a conventional one without lowering a voltage of a scanning signal to be applied to a gate bus line as compared with a conventional one. | 04-18-2013 |
20140111495 | SCANNING SIGNAL LINE DRIVE CIRCUIT, DISPLAY DEVICE HAVING THE SAME, AND DRIVING METHOD FOR SCANNING SIGNAL LINE - The purpose of this invention is to increase reliability of a switching element while reducing consumption power. In the vertical blanking period, an end pulse signal (ED) changes from the low level to the high level. The potential of first nodes (N | 04-24-2014 |
20150030116 | SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE - A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive. | 01-29-2015 |