Patent application number | Description | Published |
20100074064 | METHOD FOR ADJUSTING TILT OF OPTICAL PICK-UP HEAD - A method for adjusting a tilt of an optical pick-up head includes the steps of: moving the optical pick-up head to a first location and focusing on; obtaining a first focus control power and a first optimum tilt angle at the first location; moving the optical pick-up head to a second location and focusing on; obtaining a second focus control power and a second optimum tilt angle at the second location; calculating an optical sensitivity according to the first and second optimum tilt angles, and the first and second focus control powers; and when the head is moved to a specific location where the tilt of the head is to be adjusted, storing a focus control power corresponding to the specific location, and calculating a tilt angle corresponding to the specific location according to the focus control power and the optical sensitivity so that the tilt of the optical pick-up head can be appropriately adjusted. | 03-25-2010 |
20100135131 | METHOD FOR DETECTING BLANK AREA OF POWER CALIBRATION AREA - The present invention relates to a method for detecting a blank area of a power calibration area. The method includes the steps of: selecting a recording test area in the power calibration area; writing the recording test area with multiple stages of normal power and detecting power; forming multiple normal blocks and detecting blocks, wherein each of the detecting blocks includes one unit of unrecorded block and one unit of recorded block; and reading information from the unrecorded blocks of the detecting blocks and thus determining whether the unrecorded blocks of the detecting blocks are blank or not. Once all the unrecorded blocks of the detecting blocks are determined to be blank, it represents that the selected recording test area is totally blank. | 06-03-2010 |
20100177314 | METHODS FOR ON-LINE CALIBRATING OUTPUT POWER OF OPTICAL PICK-UP - The present invention relates to methods for on-line calibrating output power of an optical pick-up. A power adjusting circuit of the optical pick-up has an optical power regulator and an optical power detector. The on-line output power calibrating method includes the steps of: performing a recording pre-process; providing a focus offset value and/or a tilt offset value to the optical pick-up; providing a setting value, corresponding to power under test, to the optical power regulator; detecting laser power emitted from the optical pick-up using the optical power detector; comparing the laser power with the power under test to adjust the setting value of the optical power regulator corresponding to the power under test; and performing an optimum power calibration if the laser power emitted from the optical pick-up conforms to the power under test. | 07-15-2010 |
20100254239 | METHOD FOR ADJUSTING TILT OF OPTICAL PICK-UP HEAD - The present invention relates to a method for calibrating a focus position of an optical pick-up. The optical pick-up is located on a focus position at a preset distance from a recordable optical medium to emit a recording beam of a preset power to the recordable optical medium so that corresponding optical data are recorded in the recordable optical medium. The method includes: altering a focus position of the optical pick-up during a recording process to generate a corresponding write radio frequency (RF) signal; detecting a minimum value of the write RF signal and a corresponding object focus position; and moving the optical pick-up to the object focus position so that the optical pick-up performs recording at the object focus position in the recordable optical medium. | 10-07-2010 |
Patent application number | Description | Published |
20110003254 | LAYOUT DECOMPOSITION METHOD APPLICABLE TO A DUAL-PATTERN LITHOGRAPHY - A layout decomposition method, applicable to a double pattern lithography, includes the steps of: putting at least a stitch on each of a plurality of sub-patterns of an initial layout pattern at preset intervals to thereby divide the each of the plurality of sub-patterns into a plurality of unit blocks each selectively labeled as a first region or a second region such that the first region and the second region in same said sub-pattern alternate, wherein any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, are labeled as the first region and the second region, respectively; reducing the stitches of any two neighboring ones of said unit blocks attributed to any two neighboring ones of said sub-patterns, respectively, so as to generate a first layout pattern having a minimum number of stitches; and reducing the stitches of any two contiguous ones of said unit blocks of each of said sub-patterns in the first layout pattern, so as to generate a second layout pattern having a minimum number of stitches. | 01-06-2011 |
20110004858 | METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT - A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided. | 01-06-2011 |
20120110538 | CLOCK-TREE STRUCTURE AND METHOD FOR SYNTHESIZING THE SAME - A method for synthesizing a clock-tree structure may be applied to a physical design such as an integrated circuit or a printed circuit board to form a symmetrical clock-tree structure, while achieving the effects including minimizing a clock skew, having a process variation tolerance and increasing the synthesizing rate. To prevent a certain level from having too many branches and ensure that the clock-tree structure satisfies the fan-out constraint, a plurality of pseudo sinks are provided such that the result of factorizing the value of the number of the total sinks may satisfy the fan-out constraint. The levels in the clock-tree structure may have equal branch lengths by employing snaking routing, so as to achieve a symmetrical clock-tree structure design and reduce the clock skew of the clock-tree. | 05-03-2012 |
20120216167 | Routing Method for Flip Chip Package and Apparatus Using the Same - Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads. | 08-23-2012 |
20130093048 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 04-18-2013 |
20140033156 | ROUTING METHOD FOR FLIP CHIP PACKAGE AND APPARATUS USING THE SAME - Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads. | 01-30-2014 |
20140291745 | Deposited Material and Method of Formation - A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period. | 10-02-2014 |
Patent application number | Description | Published |
20100023910 | METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME - A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each corresponding to one level and k+1 packing sub-trees each corresponding to one of the nodes and comprising a group of macros, optimizing the multi-packing tree according to a packing result thereof, and generating output files in a DEF format. | 01-28-2010 |
20110202897 | HIERARCHY-BASED ANALYTICAL PLACEMENT METHOD CAPABLE OF MACRO ROTATION WITHIN AN INTEGRATED CIRCUIT - A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement. | 08-18-2011 |
20130097574 | METHOD OF ANALYTICAL PLACEMENT WITH WEIGHTED-AVERAGE WIRELENGTH MODEL - A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area. | 04-18-2013 |
20130298097 | METHOD OF IMPLEMENTING TIMING ENGINEERING CHANGE ORDER - A method of implementing timing ECO in a circuit includes the steps of performing a static timing analysis on the circuit so as to determine at least one timing violating path of the circuit, decomposing the timing violating path into at least one violating path segment, determining a smooth curve from each timing violating path and determining a plurality of reference points along the smooth curve, computing a fixability parameter of each gate on the violating path segment, extracting at least one gate according to the fixability parameters, and selecting one spare cell and disposing the selected spare cell on the violating path segment. | 11-07-2013 |
Patent application number | Description | Published |
20100149880 | WINDOW ENLARGEMENT BY SELECTIVE ERASE OF NON-VOLATILE MEMORY CELLS - A method is described for enlarging a programming window of charge trapping memory cells in a virtual ground charge trapping memory EEPROM array. The method substantially eliminates second bit effects and program disturbances to nearby charge trapping memory cells. | 06-17-2010 |
20110038208 | METHOD OF READING DUAL-BIT MEMORY CELL - A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value. | 02-17-2011 |
20110211434 | METHOD OF RECOGNIZING TRACK PITCH OF OPTICAL DISK - A method of recognizing a track pitch of an optical disk, adapted for an optical disk player, is provided. The method includes the steps of driving an optical pickup head to a predetermined position, so that the optical pickup head and the spindle motor are a predetermined distance apart, reading a data sector address, and recognizing the magnitude of the track pitch of the optical disk according to the value of the data sector address. | 09-01-2011 |
20140254280 | Programming Method For Memory Cell - A method for programming memory cells includes applying a programming voltage to a selected memory cell in a memory cell array and a neighboring passing voltage to a neighboring memory cell next to the selected memory cell, increasing the programming voltage for programming the selected memory cell, and increasing the neighboring passing voltage for programming the selected memory cell. | 09-11-2014 |
20140264378 | SEMICONDUCTOR STRUCTURE - A semiconductor structure has a MOSFET and a substrate to accommodate the MOSFET. The MOSFET has a gate, a source, and a drain in the substrate. A first substrate region surrounding the MOSFET is doped with a stress enhancer, wherein the stress enhancer is configured to generate a tensile stress in the MOSFET's channel and the tensile stress is along the channel's widthwise direction. | 09-18-2014 |
20140269054 | NON-VOLATILE MEMORY AND METHOD OF OPERATION THEREOF - A method of altering threshold voltage distribution of a non-volatile MLC memory before the memory is programmed according to a pre-designated coding table. The method includes grouping a plurality of cells which are pre-designated to have the same first bit voltage in a same main state and then grouping the cells in a selected main state into a same sub state if they have the same pre-designated second bit voltage. The method further has a step by elevating the first bit voltage of the cells with highest pre-designated second bit voltage to a voltage which is greater than the voltage of the pre-designated highest main state. | 09-18-2014 |
Patent application number | Description | Published |
20080310262 | METHOD FOR AUTOMATICALLY CALIBRATING OUTPUT POWER OF OPTICAL PICK-UP HEAD AND OPTICAL DISC DRIVER USING THE METHOD - A method for automatically calibrating an output power of an optical pick-up head is provided. First, an optical disc is provided, wherein a relationship between the output power for writing the optical disc and a specific parameter corresponding thereto is defined as a first function. Next, the optical pick-up head is controlled to perform a writing operation on the optical disc according to an instruction value, and obtain the specific parameter corresponding to the instruction value. Next, the output power corresponding to the instruction value is obtained according to the first function and the specific parameter. Next, the instruction value is adjusted according to the instruction value and the output power, and the output power of the optical pick-up head is calibrated according to the adjusted instruction value. | 12-18-2008 |
20100182882 | OPTICAL STORAGE APPARATUS AND METHOD FOR ELIMINATING WRITE POWER TRANSIENT THEREOF - An optical storage apparatus and a method for eliminating a write power transient thereof are provided. The method includes following steps. First, a target voltage level of a write voltage when next time the optical storage apparatus writes data is obtained. Then, a command value is updated by using the target voltage level according to a relationship between the command value and the write voltage. Next, the write voltage of the optical storage apparatus is pre-charged to the target voltage level according to the updated command value. Thereby, the write power transient of the optical storage apparatus can be eliminated. | 07-22-2010 |
20100188943 | OPTICAL STORAGE APPARATUS AND METHOD FOR AUTOMATICALLY ADJUSTING LOOP GAIN THEREOF - An optical storage apparatus and a method for automatically adjusting a loop gain thereof are provided. The method includes the following steps. Firstly, a compact disk is written by an erase power. Next, a writing state of the erase power is detected to generate an error signal. Finally, a loop gain of a servo control loop is corrected according to the error signal. Therefore, the loop gain can be corrected by the present invention according to a reflectance of the compact disk. | 07-29-2010 |
Patent application number | Description | Published |
20130314056 | POWER FACTOR CORRECTION APPARATUS - A power factor correction apparatus is applied to an alternating-current voltage apparatus and a rear end circuit. The power factor correction apparatus includes a power factor correction unit, a control unit, and a ripple detecting unit. The power factor correction unit is electrically connected to the rear end circuit and the alternating-current voltage apparatus. The control unit is electrically connected to the power factor correction unit. The ripple detecting unit is electrically connected to the rear end circuit, the power factor correction unit, and the control unit. The control unit is informed by the ripple detecting unit to control the power factor correction unit to adjust the power factor after the ripple of the signal outputted from the power factor correction unit is detected by the ripple detecting unit. | 11-28-2013 |
20140185330 | DC to DC POWER CONVERTING DEVICE - A power converting device includes a switching unit, a resonant unit, a converting unit, a rectifying and filtering unit, an inductance-sensing unit, and a driver. The resonant unit is electrically connected to the switching unit and includes a resonant capacitor, a resonant inductor, and a variable magnetizing-inductor having at least two inductances, the resonant inductor is electrically connected to the resonant capacitor and the variable magnetizing-inductor. The converting unit is electrically connected to the resonant unit. The rectifying and filtering unit is electrically connected to the converting unit. The inductance-sensing unit is electrically connected to the rectifying and filtering unit, the inductance-sensing unit instantaneously senses inductances of the variable magnetizing-inductor. The driver is electrically connected to the inductance-sensing unit and the switching unit, the driver is configured for controlling a switching frequency of the switching unit according to an inductance instantaneously sensed by the inductance-sensing unit. | 07-03-2014 |
20150054474 | POWER SUPPLY APPARATUS WITH REDUCING VOLTAGE OVERSHOOTING - A voltage generating unit generates a standard output voltage and sends to a voltage output side. A voltage detection unit detects a voltage of the voltage output side and informs a voltage gain control unit. When the voltage of the voltage output side is decreasing due to a dynamic load, the voltage gain control unit is configured to control the voltage generating unit to increase a gain of a voltage generated by the voltage generating unit, and the voltage generated by the voltage generating unit is lower than the standard output voltage. Then, the voltage gain control unit is configured to control the voltage generating unit to decrease the gain of the voltage generated by the voltage generating unit, and the voltage generated by the voltage generating unit is equal to the standard output voltage. | 02-26-2015 |
Patent application number | Description | Published |
20080252548 | ANTENNA STRUCTURE FOR A NOTEBOOK - An antenna structure for a notebook comprising a main body of an antenna and a printed circuit board which is provided on the main body of the antenna and is electrically connected; and the printed circuit board is laid out thereon at least with a radio frequency matched line, the radio frequency matched line can be adjusted to get a desired bandwidth. | 10-16-2008 |
20080278401 | ANTENNA STRUCTURE FOR A NOTEBOOK - An antenna structure for a notebook with four radiation members, the antenna structure has an elongate supporting rack having thereon a first radiation member, a second radiation member, a third radiation member and a fourth radiation member; each radiation member is planar, and is integrally connected with the supporting rack. Thereby, when the notebook uses a plurality of antennas, the costs of mold developing and time for processing can be reduced, and in designing, the space of the antenna will not waste by having the structure, and a better effect in function can be obtained. | 11-13-2008 |
20080309558 | MICRO ANTENNA STRUCTURE - A micro antenna structure composed of a base plate and an antenna structure, a grounding surface and a clear space are formed on the base plate. The antenna structure is provided in the clear space and includes a radiation element and a fixing plate; the fixing plate is made of material for making a printed circuit board, while the radiation element is made from copper foils and is laid out linearly on the fixing plate. With this structure, the problem of having complicated procedure of processing and high cost of a conventional micro chip antenna can be eliminated here, and a good effect can be attained by using minimum space; thereby the weight and volume of a mobile communication product can be reduced but a good effect can be attained. | 12-18-2008 |
20090102722 | INVERTED F-TYPE ANTENNA - An inverted F-type antenna, the antenna mainly comprises a low-frequency radiation arm, a high-frequency radiation arm and a main signal line; an end of the high-frequency radiation arm is connected to a grounding line, and the main signal line is extended upwards from the high-frequency radiation arm, a single signal feed-in point is provided at a connecting area of the main signal line with the high-frequency radiation arm. By forming a loop between the grounding line and the feed-in point, the antenna can provide a high frequency effect. | 04-23-2009 |
20100039349 | Dual-resonance retractable antenna - A dual-resonance retractable antenna includes a connector, a telescopic radiating device mounted on the connector, and a radiating tube mounted on the connector around the tubular outer radiating element of the telescopic radiating device and electrically isolated from the telescopic radiating device. By means of moving the telescopic radiating device between the extended position and the received position, the dual-resonance retractable antenna can oscillate at two different resonance frequencies, having multi-band multi-system capabilities for multiplex application. | 02-18-2010 |