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Yang, Zhubei City
Chang Chan Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120263002 | TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY - A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided. | 10-18-2012 |
Chen-Lin Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110292754 | MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION - A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit. | 12-01-2011 |
| 20120110530 | COMPUTER SYSTEM AND METHOD OF PREPARING A LAYOUT - The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated. | 05-03-2012 |
| 20120236675 | Methods and Apparatus for Memory Word Line Driver - A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed. | 09-20-2012 |
He-Shun Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120113675 | LAMP DEVICE WITH COLOR-CHANGEABLE FILTER - A lamp device includes a supporting frame, a light emitting diode (LED) array source, a light filter, two end caps and two couples of electrodes. The LED array source is disposed on the supporting frame. The light filter is arc-shaped and combined with the supporting frame as a tubular structure, wherein the arc surface of the light filter is a light emitting surface of the LED array source. The light filter is used for absorbing a ray in a specific wavelength range of the emitting light of the LED array source. The two end caps are disposed at two ends of the tubular structure respectively. The two couples of electrodes are disposed at two ends of the tubular structure and mounted on the two end caps respectively for electrically connecting to the LED array source. | 05-10-2012 |
Hsueh-Wei Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120293454 | METHOD OF IDENTIFYING PALM AREA FOR TOUCH PANEL AND METHOD FOR UPDATING THE IDENTIFIED PALM AREA - A method of identifying a palm area for a touch panel has steps of: receiving sensing frame information having multiple touching sensing points from the touch panel; selecting one of the touching sensing points; outwardly extending a distance from an outline of the selected touching sensing point to define a searching range; checking whether other touching sensing points are within the searching range; marking the touching sensing points in the searching range and expanding the searching range based on the currently marked touching sensing points; sequentially selecting and checking each touching sensing point if it is within the present searching range; and finally merging all the outlines of the marked touching sensing points to form a final outline as a palm area. Other unmarked touching sensing points are defined as touching reference points. | 11-22-2012 |
Jiing-Feng Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110198757 | SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME - A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region. | 08-18-2011 |
| 20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
| 20110291281 | PARTIAL AIR GAP FORMATION FOR PROVIDING INTERCONNECT ISOLATION IN INTEGRATED CIRCUITS - Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap. | 12-01-2011 |
| 20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
Jing-Hwang Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120181612 | LOW TCR HIGH RESISTANCE RESISTOR - The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height. | 07-19-2012 |
Jiun-Yan Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110115700 | System for Displaying Images - A system for displaying images includes a transflective display panel and a light source module oppositely disposed thereto. The light source module includes a light guide plate, a plurality of first light-emitting diodes (LEDs), a plurality of second LEDs, and a lighting control unit electrically connected to the pluralities of first and second LEDs. The light guide plate includes a first portion and a second portion corresponding to a first display region and a second display region of the transflective display panel, respectively. Each first LED is a white light-emitting diode and transmits an emitted light therefrom to the first display region by the first portion of the light guide plate. The plurality of second LEDs includes red, green, and blue LEDs and transmits an emitted light therefrom to the second display region by the second portion of the light guide plate. | 05-19-2011 |
| 20110286078 | FULL COLOR ELECTROPHORETIC DISPLAY DEVICE - A system for displaying images is provided. The system includes a display device including a display device having a pixel unit array. Each pixel unit is constituted by a first sub-pixel and a second sub-pixel adjoined thereto. The first sub-pixel includes a plurality of first charged colored particles and a plurality of second charged colored particles to receive a light source that doesn't pass through a color filter. The second sub-pixel includes a plurality of third charged colored particles and a plurality of fourth charged colored particles to receive the light source. The pluralities of first, second, third, and fourth charged colored particles have at least three colors in total. | 11-24-2011 |
Kuo-Yuh Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120149145 | METHOD FOR MANUFACTURING IMAGE SENSOR - A method for manufacturing an image sensor, wherein the method comprises several steps as follows: A semiconductor base doped with dopants having a first-type electrical conductivity is provided, wherein the semiconductor base comprises a handle wafer, an oxide insulator disposed on the handle wafer, and a silicon layer disposed on the oxide insulator. A front end process is then conducted, to form at least one imaging pixel disposed in the silicon layer and at least one metal layer disposed on the imaging pixel, whereby the first-type electrical dopants can be driven into the silicon layer to form a doping layer with the first-type electrical conductivity over the oxide insulator. | 06-14-2012 |
Sheng-Jier Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090282374 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 11-12-2009 |
| 20110204449 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 08-25-2011 |
| 20110291197 | INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF - An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance. | 12-01-2011 |
Shih-Hsien Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120190152 | Methods for Fabricating Integrated Passive Devices on Glass Substrates - A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers. | 07-26-2012 |
Shih-Tsung Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120086656 | Touch Sensing Circuit and Associated Method - A touch sensing circuit and method is provided. The touch sensing circuit discriminates a common voltage change of a display panel couple to the touch sensor in a touch panel display apparatus. The touch sensor comprises a plurality of sensor electrodes. The touch sensing circuit includes a plurality of channel circuits, each of which includes a reset switch and a sensing switch for alternately conducting an associated sensor electrode to a reset voltage and a charge collecting circuit. The channel circuits are divided to different groups that operate according to interleaving timings for encompassing possible common voltage changes. | 04-12-2012 |
Yun-Chi Yang, Zhubei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120166130 | METHOD FOR EVALUATING FAILURE RATE - A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips. | 06-28-2012 |