Patent application number | Description | Published |
20080237745 | SRAM CELL WITH ASYMMETRICAL TRANSISTORS FOR REDUCED LEAKAGE - A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current. | 10-02-2008 |
20080315328 | DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS - Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors. | 12-25-2008 |
20090140346 | MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS - One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed. | 06-04-2009 |
20100207183 | SRAM Cell with Asymmetrical Pass Gate - A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( | 08-19-2010 |
20120261768 | SRAM CELL WITH ASYMMETRICAL PASS GATE - A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( | 10-18-2012 |
Patent application number | Description | Published |
20080205845 | Variable Optical Attenuator - A variable optical attenuator is disclosed, which attenuates a beam of light while preserving its polarization substantially independent of wavelength. The beam of light is attenuated by a filter patterned with a grating of blocking stripes with serrated edges, which partially block and partially transmit the beam of light, respectively. The serrated edges provide for low polarization dependent loss. Along a length of the filter, a mark to space ratio of blocking stripe and aperture widths increases. By a linear translation of the filter along its length attenuation can be varied to a desired value. A stepper motor with lead screw can provide a suitable linear translation to give the filter a latching property. | 08-28-2008 |
20090103867 | Variable Optical Attenuator - A compact variable optical attenuator having optical-tap functionality is described comprising a planar waveguide attenuator, a lens, and a photodetector. Input and output waveguides are located close to the optical axis of the lens, which reduces optical aberrations and insertion loss. The waveguide attenuator works by light absorption with virtually no scattered light present, which improves fidelity of measurements of the tapped optical power by the photodetector. The entire tap-attenuator assembly is packaged into a small form pluggable (SFP) package having two optical connectors. | 04-23-2009 |
20110089314 | COMPACT TAP MONITOR - A compact PD unidirectivity solution for an optical tap monitor, which reduces the overall size of optical tap module, is provided. The solution is to use lensing to separate the light from the input and output fibres, and then add a mask or spacer in front of the monitor PD to prevent any of the light from the output fiber from entering the photodetector package. | 04-21-2011 |
Patent application number | Description | Published |
20110051341 | Datacommunications/Telecommunications Patching Systems with Integrated Connectivity Module - A module adapted for use with a datacommunications equipment mounting structure includes: a generally upright divider panel; a cover panel disposed generally parallel to the divider panel, the cover panel and divider panel being spaced apart from each other to form a gap; and a plurality of telecommunications cables, each of the telecommunications cables comprising a plurality of telecommunications patch cords, the cables comprising bundled patch cords at a first end and unbundled patch cords at a second opposite end, the cables being positioned in the gap between the divider panel and cover panel. The bundled patch cords at the cable first end include first interconnection terminals, and the unbundled patch cords at the second end include second interconnection terminals. The first terminals are located at first edges of the divider and cover panels. The unbundled patch cords are separately moveable between a stored position, in which the second terminals are located at second edges of the divider and cover panels, and an extended position, in which the second terminals are positioned away from the second edges of the divider and cover panels. | 03-03-2011 |
20120040539 | Datacommunications Modules, Cable-Connector Assemblies and Components Therefor - A combination includes: (a) a communications module including: a housing; a printed wiring board mounted within the housing; a plurality of RJ-45 jacks mounted on the printed wiring board and accessible from one side of the housing; and a single module connector mounted to the printed wiring board and electrically connected to the RJ-45 jacks, connector being accessible from a second side of the housing; and (b) a cable-connector assembly including: a cable comprising a plurality of subunits, each of the subunits comprising a jacket and a plurality of twisted pairs of conductors positioned within the jacket; and a single cable connector mounted to the printed circuit board and electrically connected to the conductors of the cable subunits. The module connector is attached to the cable connector. | 02-16-2012 |
20130266283 | DATACOMMUNICATIONS/TELECOMMUNICATIONS PATCHING SYSTEMS WITH INTEGRATED CONNECTIVITY MODULE - A module adapted for use with a datacommunications equipment mounting structure includes: a generally upright divider panel; a cover panel disposed generally parallel to the divider panel, the cover panel and divider panel being spaced apart from each other to form a gap; and a plurality of telecommunications cables, each of the telecommunications cables comprising a plurality of telecommunications patch cords, the cables comprising bundled patch cords at a first end and unbundled patch cords at a second opposite end, the cables being positioned in the gap between the divider panel and cover panel. The bundled patch cords at the cable first end include first interconnection terminals, and the unbundled patch cords at the second end include second interconnection terminals. The first terminals are located at first edges of the divider and cover panels. The unbundled patch cords are separately moveable between a stored position, in which the second terminals are located at second edges of the divider and cover panels, and an extended position, in which the second terminals are positioned away from the second edges of the divider and cover panels. | 10-10-2013 |
Patent application number | Description | Published |
20080273497 | Handover for DVB-H - A method of wireless handover in a broadcast network (FIGS. | 11-06-2008 |
20100246714 | METHOD AND SYSTEM FOR CREST FACTOR REDUCTION - An apparatus and system are provided for crest factor reduction (CFR). Preferably, a peak from the wideband signal is detected. A gain from the magnitude of the peak and a threshold can then be calculated. Based on this information, each carrier's contribution to the peak can be approximated, and a cancellation pulse coefficient for each carrier from its contribution to the peak can be calculated. A base cancellation pulse can be calculated from the cancellation pulse coefficients for each carrier, and a cancellation pulse can be calculated from the base cancellation pulse and the gain, which can then be applied to the wideband signal. | 09-30-2010 |
20110080216 | Systems and Methods of Power Amplifier Digital Pre-Distortion - Systems and methods for power amplifier pre-distortion are provided. The systems and methods of power amplifier digital pre-distortion disclosed herein may include a generic pre-distorter architecture which can implement a variety of Volterra cross terms involving single dimension convolutions (first order dynamics). For hardware implementations, this generic pre-distorter is further fine-tuned to provide a choice between different sets of cross terms that can be selected for a given PA for optimal performance. The novel pre-distorter architecture provides flexibility to trade off memory depth for additional Volterra terms and vice versa. A further novelty is the ability to trade off both memory depth and cross terms for a higher sample rate operation, which may enable higher order non-linear pre-distortion, or support for higher signal bandwidths. A poly-phase non-linear filtering mode allows for this flexibility. | 04-07-2011 |
20110090107 | TIME-INTERLEAVED-DUAL CHANNEL ADC WITH MISMATCH COMPENSATION - Previously, when designing receivers for radio frequency (RF) or wireless communications, designers chose between time-interleaved (TI) analog-to-digital converters (ADCs) for intermediate frequency architectures and dual channel ADCs for direct conversion architectures. Here, similarities between TI ADCs and dual channel ADC were recognized, and an ADC that has the capability of operating as a TI ADCs and dual channel ADC is provided. This allows designer to have greatly increased flexibility during the design process which can greatly reduce design costs, while also allowing the manufacturer of the ADC to realize a reduction in its operating costs. | 04-21-2011 |
20110158297 | JOINT TRANSMIT AND RECEIVE I/Q IMBALANCE COMPENSATION - Conventional transceivers do provide some compensation for in-phase/quadrature (I/Q) imbalance. However, these techniques do not separately compensate for I/Q imbalance for the transmitter and receiver sides of the transceiver. Here, a transceiver is provided that allows for compensation of I/Q imbalance in the transmitter and receiver irrespective of the other to allow for a more accurate transceiver. | 06-30-2011 |
20120069931 | MULTI-BAND POWER AMPLIFIER DIGITAL PREDISTORTION SYSTEM AND METHOD - Traditionally, for multi-band communication systems, independent signal chains for each of the different bands are employed. By using such an architecture, there are a large number of components, and there is substantial power consumption. Here, transmit processor is provided that enables transmission across multiple bands using few components (namely, fewer signal chains), while also provided for digital predistortion. | 03-22-2012 |
20120134399 | Systems and Methods of Improved Power Amplifier Efficiency Through Adjustments in Crest Factor Reduction - Crest factor reduction algorithms described herein may be used to improve power amplifier efficiency during low signal power conditions compared to traditional static threshold techniques. Techniques described herein insure that the signal power level at the output of the crest fact reduction block is held constant relative to the input power level under all signal power level conditions. Two different solutions may be implemented together or separately to achieve the desired conditions. The first technique provides constant ratio between input power and output power. Constant ratio of peak and average output levels keeps the amount of crest factor reduction applied to the signal constant, irrespective of the signal power level. A second technique is to hold signal power level constant in respect to the amount of crest factor reduction applied. | 05-31-2012 |
20120250790 | FREQUENCY SELECTIVE IQ CORRECTION - In conventional radio frequency (RF) systems, transmitters will usually convert baseband signals to RF so as to be transmitted. As part of the conversion process, the transmitters will perform digital preditortion (DPD), which uses feedback from a power amplifier. However, there are usually mismatches between the in-phase (I) and quadrature (Q) paths within with feedback loop. Traditional IQ correction filters were ineffective at providing adequate compensation for these mismatches, but here a filter is provided that provides adequate out-of-band compensation by use of frequency selectivity. | 10-04-2012 |
20130083834 | Power-Indexed Look-Up Table Design of Digital Pre-Distortion for Power Amplifiers with Dynamic Nonlinearities - This invention is a method of power amplifier digital pre-distortion which measures a current power level of the power amplifier, stores in a look up table entries consisting of a power level and a corresponding set of digital pre-distortion coefficients, selects a set of digital pre-distortion coefficients corresponding to the measured power level. If the measured current power level is near a power level index, the digital pre-distortion coefficients correspond to the power level index. If the measured current power level is greater than the maximum power level entry, the digital pre-distortion coefficients is of the maximum power level entry. If the measured current power level is less than the minimum power level entry, the digital pre-distortion is of the minimum power level entry. If the measured current power level is not near a power level index, the digital pre-distortion coefficients are an interpolation. | 04-04-2013 |
20140140452 | CREST FACTOR REDUCTION FOR SIGNALS WITH DYNAMIC POWER AND FREQUENCY DISTRIBUTION - A method to form a CFR cancellation filter for signals with dynamic power and frequency distribution by estimating the filter at the rate required by the input signal's dynamics. For mixed mode systems (for example CDMA and LTE) the CFR is computed for each stream, and combined to form the final filter. | 05-22-2014 |
20140169496 | Crest Factor Reduction for Multi-Band System - Systems and methods for crest factor reduction (CFR) are described. A multi-band CFR architecture achieves significant hardware savings without sacrificing CFR performance by applying peak cancellation to each band individually. However, peak detection is calculated based on a combined input signal. | 06-19-2014 |
20140294120 | DUAL LOOP DIGITAL PREDISTORTION FOR POWER AMPLIFIERS - A method of predistorting an input signal ( | 10-02-2014 |
20150030099 | CIRCUITS AND METHODS FOR REDUCING THE AMPLITUDE OF COMPLEX SIGNALS - For crest factor reduction in a first signal having first and second components, the first component is delayed. A second signal is generated in response to detecting that a peak in the first component exceeds a predetermined threshold. Amplitude of the peak in the first component is reduced in response to detecting that the peak in the first component exceeds the predetermined threshold. Reducing amplitude of the peak in the first component includes adding the second signal to the delayed first component. | 01-29-2015 |
20150085748 | SYSTEM AND METHOD FOR CONTROLLING PEAK TO AVERAGE POWER RATIO - A system and method for reducing peak to average power ratio in a wireless communication system. A wireless communication system includes a radio frequency wireless transmitter that includes signal peak reduction circuitry configured to reduce peak to average power ratio of a signal to be transmitted by reducing amplitude of the signal to be transmitted that is greater than a predetermined amplitude. The signal peak reduction circuitry includes a bit inverter configured to invert a bit of a symbol identified as causing the amplitude of the signal to exceed the predetermined amplitude. The bit inverter is also configured to select the bit to invert such that inversion of the bit reduces the amplitude of the signal, and such that forward error correction in a receiver wirelessly coupled to the transmitter restores the bit to a pre-inversion value. | 03-26-2015 |
20150214988 | DUAL LOOP DIGITAL PREDISTORTION FOR POWER AMPLIFIERS - A method of predistorting an input signal ( | 07-30-2015 |
20150236730 | subtracting linear impairments for non-linear impairment digital pre-distortion error signal - Example embodiment of the systems and methods of linear impairment modeling to improve digital pre-distortion adaptation performance includes a DPD module that is modified during each sample by a DPD adaptation engine. A linear impairment modeling module separates the linear and non-linear errors introduced in the power amplifier. The linear impairment model is adjusted during each sample using inputs from the input signal and from a FB post processing module. The linear impairment modeling module removes the linear errors such that the DPD adaptation engine only adapts the DPD module based on the non-linear errors. This increases system stability and allows for the correction of IQ imbalance inside the linear impairment modeling, simplifying the feedback post-processing. | 08-20-2015 |
20160065249 | CAPTURE SELECTION FOR DIGITAL PRE-DISTORTION ADAPTATION AND CAPTURE CONCATENATION FOR FREQUENCY HOPPING PRE-DISTORTION ADAPTATION - A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a first change matrix associated with a portion of the first sample set of data; a first memory component that stores the first change matrix; a second capturing component that captures a second sample set of data; a second generating component that generates a second change matrix associated with a portion of the second sample set of data; a second memory component that stores the second change matrix; a third capturing component that captures a third sample set of data; a third generating component that generates a third change matrix associated with a portion of the third sample set of data; a comparing component that compares the third change matrix with the first change matrix to obtain a first comparison, and compares the third change matrix with the second change matrix to obtain a second comparison; and an adapting component that adapts the digital pre-distortion component with the third sample set of data based on one of the first comparison and the second comparison. | 03-03-2016 |