Patent application number | Description | Published |
20120300332 | Systems and Methods for Data Addressing in a Storage Device - Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output. | 11-29-2012 |
20120330584 | Systems and Methods for Power Monitoring in a Variable Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data detector circuit, a data decoder circuit, and a power monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoded output to yield a detected output. The data decoder circuit is operable to apply a data decoding algorithm to the detected output to yield the decoded output. The power monitor circuit is operable to receive a first power status signal from the data detector circuit and a second power status from the data decoder circuit, and to calculate a power usage of a combination of at least the data detector circuit and the data decoder circuit. In such a system, a number of global iterations through a combination of the data decoder circuit and the data detector circuit is variable and both of the first power status signal and the second power status signal varies at least in part as a function of the number of global iterations. | 12-27-2012 |
20120331363 | Systems and Methods for Reduced Format Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector. | 12-27-2012 |
20120331370 | Systems and Methods for Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output. | 12-27-2012 |
20130007551 | Stochastic Stream Decoding of Binary LDPC Codes - Various embodiments of the present invention provide systems and methods for stochastic stream decoding of binary LDPC codes. For example, a data decoder circuit is discussed that includes a number of variable nodes and check nodes, with serial connections between the variable nodes and the check nodes. The variable nodes are each operable to perform a real-valued computation of a variable node to check node message for each neighboring check node. The check nodes are operable to perform a real-valued computation of a check node to variable node message for each neighboring variable node. The messages are passed iteratively between the variable nodes and the check nodes. | 01-03-2013 |
20130063835 | Systems and Methods for Generating Predictable Degradation Bias - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data. | 03-14-2013 |
20130067247 | Systems and Methods for Governing Power Usage in an Iterative Decoding System - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit. | 03-14-2013 |
20130067297 | Systems and Methods for Non-Binary Decoding Biasing Control - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols. | 03-14-2013 |
20130080844 | Systems and Methods for Efficient Data Shuffling in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space. | 03-28-2013 |
20130111289 | SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING | 05-02-2013 |
20130111290 | Systems and Methods for Ambiguity Based Decode Algorithm Modification | 05-02-2013 |
20130139022 | Variable Sector Size LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data. | 05-30-2013 |
20130139023 | Variable Sector Size Interleaver - Various embodiments of the present invention are related to methods and apparatuses for interleaving data, and more particularly to methods and apparatuses for interleaving variably sized blocks of data. For example, in one embodiment an apparatus includes a data partitioner operable to partition the block of data into a real data portion and a missing bits portion. The real data portion is adapted to contain data bits from the variably sized block of data and the missing bits portion is adapted to be filled with a variable number of the data bits. The apparatus also includes at least one local interleaver operable to apply a permutation across each of a plurality of sub-portions of the real data portion and the missing bits portion, and a global interleaver operable to apply a global permutation across the real data portion. | 05-30-2013 |
20130148232 | Systems and Methods for Combined Binary and Non-Binary Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit. | 06-13-2013 |
20130151923 | Systems and Methods for Scalable Data Processing Shut Down - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 06-13-2013 |
20130159634 | Systems and Methods for Handling Out of Order Reporting in a Storage Device - Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device. | 06-20-2013 |
20130173932 | Systems and Methods for Decimation Based Over-Current Control - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active. | 07-04-2013 |
20130205146 | Systems and Methods for Power Governance in a Data Processing Circuit - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-08-2013 |
20130219233 | Systems and Methods for Quality Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 08-22-2013 |
20130232155 | Systems and Methods for Out of Order Data Reporting - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for out of order reporting of results from data processing. | 09-05-2013 |
20130232360 | Data Processing System with Thermal Control - Various embodiments of the present invention provide systems and methods for a data processing system with thermal control. For example, a data processing system with thermal control is disclosed that includes a number of data processors and a scheduler, which is operable to determine the power consumption of the data processors and to switch the data processing system from a first mode to a second mode and from the second mode to a third mode. The data processing system consumes less power in the third mode than in the first mode. The second mode prepares the data processing system to enter the third mode. | 09-05-2013 |
20130232390 | Systems and Methods for Multi-Matrix Data Processing - The present inventions are related to systems and methods for data processing. As one example, a data processing system is discussed that includes a data decoder circuit and a matrix select control circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input using a selected parity check matrix to yield a decoder output. The matrix select control circuit operable to select one of a first parity check matrix and a second parity check matrix as the selected parity check matrix. | 09-05-2013 |
20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 09-19-2013 |
20130246888 | Systems and Methods for Out of Order Processing in a Data Retry - Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in order. | 09-19-2013 |
20130254619 | Systems and Methods for Mis-Correction Correction in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system. | 09-26-2013 |
20130263147 | Systems and Methods for Speculative Read Based Data Processing Priority - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 10-03-2013 |
20130283114 | Systems and Methods for Locating and Correcting Decoder Mis-Corrections - Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit. | 10-24-2013 |
20130290806 | Systems and Methods for Data Decoder State Preservation During Extended Delay Processing - The present invention is related to systems and methods for maintaining additional processing information during extended delay processing. | 10-31-2013 |
20130322578 | Systems and Methods for Data Processing Including EET Feedback - The present invention is related to systems and methods for data processing system characterization. | 12-05-2013 |
20130326302 | Error Injection for LDPC Retry Validation - The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation circuit in the data processing circuit is operable to inject errors in the data set to trigger the at least one retry feature. | 12-05-2013 |
20130335850 | Initialization for Decoder-Based Filter Calibration - Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients. | 12-19-2013 |
20130339827 | Adaptive Calibration of Noise Predictive Finite Impulse Response Filter - Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold. | 12-19-2013 |
20130343495 | APPARATUS AND METHOD FOR BREAKING TRAPPING SETS - An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value. | 12-26-2013 |
20140025904 | Systems and Methods for Gate Aware Iterative Data Processing - The present invention is related to systems and methods for iterative data processing scheduling. | 01-23-2014 |
20140053038 | Method for Selecting a LDPC Candidate Code - A method for estimating error probability of LDPC codes includes ordering LDPC codes according to features in each code with known error characteristics. The method includes identifying features in each LDPC code having known error characteristics; adding each code to one or more categories based on the existence of such features; and ranking the LDPC codes according to the level of error risk. | 02-20-2014 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 02-27-2014 |
20140068372 | Systems and Methods for Local Iteration Randomization in a Data Decoder - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit. | 03-06-2014 |
20140068394 | SYSTEMS AND METHODS FOR SECTOR QUALITY DETERMINATION IN A DATA PROCESSING SYSTEM - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination. | 03-06-2014 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140095955 | Efficient Way to Construct LDPC Code by Comparing Error Events Using a Voting Based Method - A method for ordering trapping sets to find one or more dominant trapping sets includes analyzing a trapping set and a random set of codewords to generate a distance value for each trapping set, and ordering the trapping sets by the distance value. Distance values may be determined for each trapping set by tracking a vote count wherein a correct decode at a certain noise level produces a “right” vote and an incorrect decode at a certain noise level produces a “left” vote. A certain threshold number of “left” votes terminates processing at that noise level. | 04-03-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140200849 | DIVERSITY LOOP DETECTOR WITH COMPONENT DETECTOR SWITCHING - Aspects of the disclosure pertain to a system and method for providing component detector switching for a diversity loop detector. Switching between component detectors is performed via one of: a periodic state likelihood reset process, a slope-based switching process, or a cross-over connection process. The joint decision circuit switches among component detectors to promote improved performance with present of constant or transition phase offset. | 07-17-2014 |
20140223259 | Memory Architecture for Layered Low-Density Parity-Check Decoder - A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. | 08-07-2014 |
20140362463 | Timing Error Detector with Diversity Loop Detector Decision Feedback - Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset. | 12-11-2014 |