Patent application number | Description | Published |
20080277311 | Packaging Box for Medicaments - A packaging box for medicaments, which can comprise: a bottom panel ( | 11-13-2008 |
20090085905 | GAMMA-VOLTAGE GENERATION DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE - The present invention relates to a Gamma-voltage generation device and a Liquid Crystal Display (LCD) device, wherein the Gamma-voltage generation device comprises: a voltage series generation unit for generating a plurality of groups of voltage series; and a multi-path selection unit for selecting one voltage value from each group of voltage series, respectively, according to a voltage selection signal and outputting the same to generate a needed Gamma-voltage series. The LCD device comprises a display panel, a row driver and a column driver, a timing controller, an image analyzing and processing unit, and a Gamma-voltage series generation device. The present invention achieves dynamic Gamma-voltage generation by choosing among a plurality of groups of voltages to output the needed Gamma-voltage series. Further, the plurality of groups of Gamma-voltage series could be obtained with resistor networks and such devices in the existing art as DAC and the like are unnecessary, thereby the response rate is improved and the cost is reduced. | 04-02-2009 |
20090256791 | METHOD AND A DEVICE FOR COMPENSATING RESPONSE TIME OF LIQUID CRYSTAL DISPLAY - The present invention relates to a method for compensating response time of liquid crystal display and a device therefor. The compensating method comprises: receiving gray scale data of a picture in present frame and obtaining a first additional driving value according to the comparison result between gray scale data of the picture in present frame and gray scale data of the picture in previous frame; collecting the temperature value of liquid crystal layer and obtaining a temperature driving value according to said temperature value; and generating a second driving value that is applied to pixels according to the first additional driving value and the temperature driving value. The compensating device comprises: a first additional driving value module for obtaining a first additional driving value; a temperature driving value module for collecting the temperature value of liquid crystal layer and obtaining a temperature driving value according to said temperature value; and a second additional driving value module for generating a second additional driving value. The present invention can effectively reduce the response time of liquid crystal display and mitigate the streaking problem. | 10-15-2009 |
20100090986 | MULTI-TOUCH POSITIONING METHOD AND MULTI-TOUCH SCREEN - The present invention relates to a multi-touch positioning method and a multi-touch screen. The multi-touch positioning method comprising: emitting, by a first infrared ray generator set at a first angle of a display panel, infrared rays at a first wavelength; emitting, by a second infrared ray generator set at a second angle, infrared rays at a second wavelength; receiving the infrared rays of the first wavelength and generating a first infrared ray image by a first infrared ray image sensor set at an opposite angle of the first angle; receiving the infrared rays of the second wavelength and generating a second infrared ray image by a second infrared ray image sensor set at an opposite angle of the second angle; and performing processings for the first infrared ray image and the second infrared ray image to determine at least one touch point. | 04-15-2010 |
20100238390 | LIQUID CRYSTAL PANEL AND MANUFACTURING METHOD THEREOF - The embodiment of the invention provides a liquid crystal panel, comprising a color filter substrate, an array substrate and a layer of liquid crystal molecules interposed between the color filter substrate and the array substrate. The color filter substrate includes a black matrix, color filters, a protection layer and a common electrode formed a substrate, and cut-off patterns used to decrease motion speeds of impurity ions are formed in the common electrode so as to suppress image sticking. | 09-23-2010 |
20140035955 | DISPLAY METHOD, DISPLAY DEVICE AND DISPLAY SYSTEM - A display device comprises a timing controller (TCON), a scaler, a buffer and a comparator; the comparator is used for comparing whether pixel data of a current frame image from the scaler are identical with pixel data stored in the buffer or not; in the case where the comparison result is “identical”, the scaler enters an off-operating state; and the TCON is used for acquiring pixel data of the current frame image to be displayed and outputting the pixel data for display. A display method and a display system for the display device are provided as well. | 02-06-2014 |
20140085268 | MULTI-TOUCH POSITIONING METHOD AND MULTI-TOUCH SCREEN - The present invention relates to a multi-touch positioning method and a multi-touch screen. The multi-touch positioning method comprising: emitting, by a first infrared ray generator set at a first angle of a display panel, infrared rays at a first wavelength; emitting, by a second infrared ray generator set at a second angle, infrared rays at a second wavelength; receiving the infrared rays of the first wavelength and generating a first infrared ray image by a first infrared ray image sensor set at an opposite angle of the first angle; receiving the infrared rays of the second wavelength and generating a second infrared ray image by a second infrared ray image sensor set at an opposite angle of the second angle; and performing processings for the first infrared ray image and the second infrared ray image to determine at least one touch point. | 03-27-2014 |
Patent application number | Description | Published |
20090184378 | STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE - A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor. | 07-23-2009 |
20090236676 | STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE - The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor. | 09-24-2009 |
20090294923 | Structure and Method for Reducing Threshold Voltage Variation - A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage. | 12-03-2009 |
20110298060 | INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK - A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface. | 12-08-2011 |
20120043622 | PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE - Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state. | 02-23-2012 |
20120104469 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 05-03-2012 |
20120139062 | SELF-ALIGNED CONTACT COMBINED WITH A REPLACEMENT METAL GATE/HIGH-K GATE DIELECTRIC - A method of forming a semiconductor device is provided that includes forming a replacement gate structure on portion a substrate, wherein source regions and drain regions are formed on opposing sides of the portion of the substrate that the replacement gate structure is formed on. An intralevel dielectric is formed on the substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the substrate. A high-k dielectric spacer is formed on sidewalls of the opening, and a gate dielectric is formed on the exposed portion of the substrate. Contacts are formed through the intralevel dielectric layer to at least one of the source region and the drain region, wherein the etch that provides the opening for the contacts is selective to the high-k dielectric spacer and the high-k dielectric capping layer. | 06-07-2012 |
20120168874 | STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC - Threshold voltage controlled semiconductor structures are provided in which a conformal nitride-containing liner is located on at least exposed sidewalls of a patterned gate dielectric material having a dielectric constant of greater than silicon oxide. The conformal nitride-containing liner is a thin layer that is formed using a low temperature (less than 500° C.) nitridation process. | 07-05-2012 |
20130087859 | Work Function Adjustment By Carbon Implant In Semiconductor Devices Including Gate Structure - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 04-11-2013 |
20130099313 | FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE - FinFET structures and methods of manufacturing the FinFET structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a FinFET structure to induce Vt shift. The oxygen anneal process is performed after sidewall pull down and post silicide. | 04-25-2013 |
20130105894 | THRESHOLD VOLTAGE ADJUSTMENT FOR THIN BODY MOSFETS | 05-02-2013 |
20130105896 | Threshold Voltage Adjustment For Thin Body Mosfets | 05-02-2013 |
20130175641 | REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE - In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor. | 07-11-2013 |
20130187244 | PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE - Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k dielectric metal gate structure includes applying a current to a gate contact of the high-k dielectric metal gate structure to raise a temperature of a metal forming a gate stack. The temperature is raised beyond a Vt shift temperature threshold for providing an on-state. | 07-25-2013 |
20130191047 | ON-CHIP POLY-TO-CONTACT PROCESS MONITORING AND RELIABILITY EVALUATION SYSTEM AND METHOD OF USE - An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage. | 07-25-2013 |
20140001570 | COMPOSITE HIGH-K GATE DIELECTRIC STACK FOR REDUCING GATE LEAKAGE | 01-02-2014 |
20140061857 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 03-06-2014 |
20140065807 | PARTIALLY-BLOCKED WELL IMPLANT TO IMPROVE DIODE IDEALITY WITH SiGe ANODE - A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction. | 03-06-2014 |
20140117420 | SEMICONDUCTOR STRUCTURE INCORPORATING A CONTACT SIDEWALL SPACER WITH A SELF-ALIGNED AIRGAP AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE - Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts. | 05-01-2014 |
20140187028 | Concurrently Forming nFET and pFET Gate Dielectric Layers - Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region. | 07-03-2014 |
20140246727 | WORK FUNCTION ADJUSTMENT BY CARBON IMPLANT IN SEMICONDUCTOR DEVICES INCLUDING GATE STRUCTURE - A device including a p-type semiconductor device and an n-type semiconductor device on a semiconductor substrate. The n-type semiconductor device includes a gate structure having a high-k gate dielectric. A carbon dopant in a concentration ranging from 1×10 | 09-04-2014 |
20140264591 | METHOD AND STRUCTURE FOR DIELECTRIC ISOLATION IN A FIN FIELD EFFECT TRANSISTOR - A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants. | 09-18-2014 |
20150069513 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 03-12-2015 |
20150072481 | SEMICONDUCTOR-ON-INSULATOR DEVICE INCLUDING STAND-ALONE WELL IMPLANT TO PROVIDE JUNCTION BUTTING - A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths. | 03-12-2015 |
Patent application number | Description | Published |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 10-06-2011 |
20120286366 | Field Effect Transistor Device and Fabrication - In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET. | 11-15-2012 |
20130171813 | FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 07-04-2013 |