Yamashita, Kawasaki
Hideo Yamashita, Kawasaki JP
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20080282136 | Parity generation circuit, counter circuit, and counting method - A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit. | 11-13-2008 |
20090063830 | DEBUGGING MECHANISM FOR A PROCESSOR, ARITHMETIC OPERATION UNIT AND PROCESSOR - A debugging mechanism equipped within a processor and receiving, as inputs, respective pieces of arithmetic operation data related to a plurality of arithmetic units comprised within the processor, and receiving, as inputs, respective control signals used for the respective arithmetic operations, comprising: an unit which comprises a counter performing a counting operation synchronously with the arithmetic operation and comprises a plurality of OR circuits each receiving, as inputs, any of the respective control signals and a signal that is output when the counter value of the counter is a specific counter value; and a debug storage unit which comprises a plurality of storage units each receiving any of the respective pieces of arithmetic operation data, any of the respective outputs of the individual OR circuits, and the counter value, and each storing the arithmetic operation data and counter value when the output of the input OR circuit is valid. | 03-05-2009 |
20100088572 | PROCESSOR AND ERROR CORRECTING METHOD - A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register. | 04-08-2010 |
20110089579 | MULTI-CHIP MODULE - A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board. | 04-21-2011 |
Hiroyasu Yamashita, Kawasaki JP
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20100032552 | OPTICAL SEMICONDUCTOR DEVICE - An optical semiconductor device includes a lower electrode layer formed over a semiconductor substrate, an infrared absorption layer formed over the lower electrode layer | 02-11-2010 |
Makoto Yamashita, Kawasaki JP
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20160094305 | OPTICAL TRANSMISSION APPARATUS AND OPTICAL TRANSMISSION SYSTEM - An optical transmission apparatus including: an attenuator that attenuates a power of a first optical signal generated in a first modulation method to a first target level and attenuates a power of a second optical signal generated in a second modulation method, a modulation level in the second modulation method being lower than the modulation level in the first modulation method, to a second target level, the second target level being lower than the first target level; and a transmitter that sends a WDM signal including the first optical signal and the second optical signal that have been attenuated by the attenuator. | 03-31-2016 |
Naoto Yamashita, Kawasaki JP
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20100181176 | ILLUMINATING STRUCTURE OF KEY OPERATING UNIT, ELECTRONIC APPARATUS, PORTABLE APPARATUS, AND ILLUMINATING METHOD OF KEY OPERATING UNIT - An illuminating structure of a key operating unit for operating a key switch includes a housing unit to have a window portion formed correspondingly to the key switch, a circuit substrate to be provided inside the housing unit, to be disposed with the key switch, and to be provided with a light-guiding window portion, a keypad unit to include a key top portion inserted in the window portion of the housing unit, the keypad unit including a light-guiding portion at least in the key top portion, a light-emitting element to be arranged on a back surface side of the circuit substrate, and an illuminating plate to have a reflecting portion reflecting outgoing light of the light-emitting element to apply the reflected light from the reflecting portion to the keypad unit through the light-guiding window portion of the circuit substrate. | 07-22-2010 |
Ryoichi Yamashita, Kawasaki JP
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20100077369 | LAYOUT DESIGN METHOD, APPARATUS AND STORAGE MEDIUM - A layout design support apparatus divides a first module obtained by dividing a semiconductor integrated circuit into a plurality of second modules in order to support a layout design for determining the disposition of each cell constituting the semiconductor integrated circuit and wiring, and makes the detailed design of a layout for determining the disposition of each cell in the second module and wiring for each second module. | 03-25-2010 |
20110239178 | LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM - A layout design apparatus that designs a layout of a semiconductor integrated circuit having a plurality of layers, the apparatus includes an extractor configured to extract, when given a lower module used at multiple locations inside an upper module, information regarding upper layer wiring near respective placement locations where the lower module is placed, and a layout design unit configured to lay out the lower module by setting prohibited wiring regions in a layout database based on the upper layer wiring information extracted from multiple locations. The prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module. | 09-29-2011 |
Satoshi Yamashita, Kawasaki JP
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20090279200 | STORAGE DEVICE, CONTROL CIRCUIT FOR STORAGE DEVICE, AND SERVO-WRITE-MODE IDENTIFYING METHOD - A servo-mark search control unit detects in a magnetic disk a servo mark matching a servo mark selected by a servo-mark candidate selecting unit. In this case, according to an instruction from a servo-mark search control unit, a non-volatile memory managing unit writes servo-write-mode identification information corresponding to the detected servo mark in a servo-write-mode identification-information storage unit of a non-volatile memory. In this manner, a magnetic disk device can recognize by itself a servo write mode with which servo patterns were written in a magnetic disk included in the magnetic disk device. | 11-12-2009 |
Tomonori Yamashita, Kawasaki JP
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20120089580 | UPDATE MANAGEMENT APPARATUS, UPDATE MANAGEMENT METHOD, AND COMPUTER-READABLE MEDIUM STORING UPDATE MANAGEMENT PROGRAM - In an update management apparatus, a detection unit detects an update of one or more kinds of data included in a data set stored in a storage unit. A management unit generates a symbol sequence including a plurality of symbols corresponding to the respective plural kinds of data, and stores the symbol sequence as information indicating a version of the data set. The management unit modifies the symbol sequence indicating the previous version to change a symbol Q | 04-12-2012 |