Patent application number | Description | Published |
20120188376 | SYSTEM AND METHOD FOR ACTIVATING CAMERA SYSTEMS AND SELF BROADCASTING - A system for monitoring the operation of a vehicle. The system comprises a plurality of sensors; a plurality of optical capture devices; a memory in which at least a recording schema is stored, the at least recording schema contains rules for operation of at least one of the plurality of optical capture devices responsive of at least one of the plurality of sensors respective of at least one activity to be captured; and a recorder coupled to the plurality of sensors, the plurality of optical capture devices and the memory, the recorder determines based on the at least recording schema and responsive of at least an input from at least one of the plurality of sensors which of the at least one of the plurality of optical capture devices to operate. | 07-26-2012 |
20130080098 | Object Processing State Sensing Using RF Radiation - An apparatus for determining a correlation of a processing state of an object with RF feedback received from an energy application zone during processing of the object in the energy application zone may include at least one detector configured to detect the RF feedback from the energy application zone. The apparatus may also include at least one controller configured to receive from the at least one detector the RF feedback; receive an indication of one or more processing states of the object (e.g., as indicated by at least one processing state indicator); and determine a correlation between the received RF feedback and the one or more processing states. | 03-28-2013 |
20130248521 | DEVICE AND METHOD FOR APPLYING ELECTROMAGNETIC ENERGY TO A CONTAINER - Some aspects of the invention may be directed to an apparatus and method for applying RF energy to containers. The containers (e.g., pots, tanks, vats, kettles, reactors, etc.) may contain an object to be heated or processed by EM energy. The object may be in the liquid phase, gas phase, solid phase or any combination of phases thereof. The apparatus may comprise an outer housing. Optionally the outer housing may be substantially opaque to RF energy. The apparatus may further comprise an inner housing disposed at least partially within the outer housing, wherein at least a portion of the inner housing is configured to transmit RF energy. The apparatus may include at least one radiating element configured to apply RF energy to an energy application zone within the inner housing. In some embodiments the at least one radiating element is located external to the inner housing, optionally between the inner housing and the outer housing. In some embodiments, the at least one radiating element may be activated and RF energy may be transmitted, via the at least one activated radiating element, to the object located within the energy application zone. | 09-26-2013 |
20140247060 | OBJECT PROCESSING STATE SENSING USING RF RADIATION - A method for applying RF energy to detect a processing state of an object placed in an energy application zone, during processing of the object, may include applying RF energy to the object during processing. The method may also include receiving computed RF feedback, correlated with one or more processing states of the object; and monitoring the computed RF feedback during the processing to detect the one or more processing states of the object. | 09-04-2014 |
Patent application number | Description | Published |
20090133005 | METHOD FOR VALIDATION OF BINARY CODE TRANSFORMATIONS - A method of validating binary code transformation in one aspect includes analyzing original program and transform program. Control flow graphs are generated for both programs. The two graphs are traversed to create respective linear invariant representations. The linear representations are compared to identify incorrect transformations. | 05-21-2009 |
20090193402 | Iterative Compilation Supporting Entity Instance-Specific Compiler Option Variations - Optimizing a computer program by setting a first compiler optimization configuration for a first entity of a computer program, setting a second compiler optimization configuration for a second entity of the computer program, where the first and second entities are of the same type and where the first and second compiler optimization configurations differ, and compiling the computer program in accordance with the compiler optimization configurations, thereby creating a compiled program. | 07-30-2009 |
20110093682 | METHOD AND APPARATUS FOR PACKING DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element. | 04-21-2011 |
20110219214 | Microprocessor having novel operations - A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation. | 09-08-2011 |
20110252408 | PERFORMANCE OPTIMIZATION BASED ON DATA ACCESSES DURING CRITICAL SECTIONS - Detecting optimization opportunities is enabled by utilizing a trace of a target concurrent computer program and determining a relation between data objects accessed during the tracked execution. The relation may be stored in a Temporal Relation Graph (TRG), in an extended-TRG or another data structure. The relation may be affected by temporally-adjacent accesses to data objects. The relation may further be affected by accesses to data objects performed during critical sections of the target program. | 10-13-2011 |
20110283152 | DETECTING AND OPTIMIZING FALSE SHARING - Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined. | 11-17-2011 |
20120078925 | SEARCHING WITHIN LOG FILES - A search tool may search a text file for entries matching one or more search criterions. The search tool may parse the file into entries. Entries may be parsed into lines and fields. A search criterion may define possible content in two or more fields and relationship between the two or more fields. The search criterion may be defined based on an exemplary entry of the text file, such as for example based on a selection of fields of the exemplary entry by a user. | 03-29-2012 |
20120198210 | Microprocessor Having Novel Operations - A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation. | 08-02-2012 |
20130067192 | Data Object Profiling During Program Execution - Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object. | 03-14-2013 |
20130117537 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117538 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117539 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117540 | METHOD AND APPARATUS FOR UNPACKING PACKED DATA - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130117547 | Method and Apparatus for Unpacking and Moving Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-09-2013 |
20130124830 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124831 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124832 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124833 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124834 | Method and Apparatus for Unpacking Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20130124835 | Method and Apparatus for Packing Packed Data - An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element. | 05-16-2013 |
20140025997 | Test Selection - Computer-implemented method, computerized apparatus and a computer program product for test selection. The computer-implemented method comprising: obtaining a test suite comprising a plurality of tests for a Software Under Test (SUT); and selecting a subset of the test suite, wherein the subset provides coverage of the SUT that correlates to a coverage by a workload of the SUT, wherein the workload defines a set of input events to the SUT thereby defining portions of the SUT that are to be invoked during execution. | 01-23-2014 |
20150310332 | Predicting outcome based on input - A method, system and product for predicting an outcome of a program based on input. The method comprising: obtaining an input to be used by a program prior to executing the program; predicting by, a machine learning module, a predicted outcome of the program based on the input; wherein the predicted outcome is selected from the group consisting of: a pass outcome and a fail outcome, wherein the pass outcome is the program executing without failing when using the input, and wherein the fail outcome is the program failing when using the input. | 10-29-2015 |