| Patent application number | Description | Published |
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| 20090101915 | PHOTO SENSOR AND FABRICATION METHOD THEREOF - A photo sensor includes a patterned shielding conductive layer disposed on a transparent substrate, and a buffer dielectric layer, a patterned semiconductor layer, and a dielectric layer disposed on the patterned shielding layer in order. The patterned semiconductor layer includes an intrinsic region, a first doped region, and a second doped region, wherein the first and second doped regions are positioned at two sides of the intrinsic region separately. A patterned transparent conductive layer is disposed on the dielectric layer and covers the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region. The patterned transparent conductive layer is electrically connected to the patterned shielding conductive layer. | 04-23-2009 |
| 20090242959 | Flash Memory Cell - A flash memory cell is disclosed in the specification and drawing. The flash memory cell is described and shown with at least one floating gate heavily doped with P-type ions. | 10-01-2009 |
| 20090283772 | PHOTO SENSITIVE UNIT AND PIXEL STRUCTURE AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME - A pixel structure suitable for being disposed on a substrate is provided. The pixel structure includes a display unit and a photo sensitive unit. The display unit includes an active device and a pixel electrode. The active device is disposed on the substrate, and the pixel electrode is electrically connected to the active device. The photo sensitive unit includes a photocurrent readout unit, a shielding electrode, a photosensitive dielectric layer, and a transparent electrode. The shielding electrode is electrically connected to the photocurrent readout unit, and the photosensitive dielectric layer is disposed on the shielding electrode. The transparent electrode is disposed on the photosensitive dielectric layer that is interposed between the shielding electrode and the transparent electrode. | 11-19-2009 |
| 20090289920 | OPTICAL REFLECTED TOUCH PANEL AND PIXELS AND SYSTEM THEREOF - An optical reflective touch panel and pixels and a system thereof are provided. Each pixel of the optical reflective touch panel includes a display circuit and a sensing circuit. The display circuit controls the display of the pixel. The sensing circuit is coupled to the display circuit for sensing a sensitization state of the pixel during a turned-on period and a turned-off period of a backlight module and outputting a digital signal to notify an optical reflective touch panel system that whether the pixel is touched or not. | 11-26-2009 |
| 20090323387 | One-Time Programmable Memory and Operating Method Thereof - A one-time programmable memory cell is provided, the one-time programmable memory cell comprises: a gate dielectric layer disposed on a well; a gate electrode disposed on the gate dielectric layer; source/drain regions disposed in the well at the sides of the gate electrode, respectively; a first salicide layer disposed on one of the source/drain regions; a capacitive dielectric layer disposed on the gate electrode and the other of the source/drain regions; a first conductive plug disposed on the first salicide layer; and a second conductive plug disposed on the capacitive dielectric layer. The size of the first conductive plug is different form the size of the second conductive plug. | 12-31-2009 |
| 20110026297 | VARIABLE AND REVERSIBLE RESISTIVE ELEMENT, NON-VOLATILE MEMORY DEVICE AND METHODS FOR OPERATING AND MANUFACTURING THE NON-VOLATILE MEMORY DEVICE - A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification. | 02-03-2011 |
| 20110165727 | METHOD OF FABRICATING PHOTO SENSOR - A method of fabricating a photo sensor includes the following steps. First, a substrate is provided, having a conductive layer, a buffer dielectric layer, a patterned semiconductor layer, a dielectric layer, and a planarization layer disposed thereon from bottom to top, wherein the patterned semiconductor layer comprises a first doped region, an intrinsic region, and a second doped region disposed in order. Then, the planarization layer is patterned to form an opening in the planarization layer to expose a portion of the dielectric layer, wherein the opening is positioned on the intrinsic region and portions of the first and the second doped regions. Thereafter, at least a patterned transparent conductive layer is formed in the opening, covering the boundary of the intrinsic region and the first doped region and the boundary of the intrinsic region and the second doped region. | 07-07-2011 |
| 20110210385 | Non-volatile Semiconductor Device, Programmable Memory, Capacitor and Metal Oxide Semiconductor - A non-volatile semiconductor device, a programmable memory device, a capacitor and a metal oxide semiconductor are disclosed, wherein the non-volatile semiconductor device includes a gate dielectric layer, a floating gate, a coupling gate, a source and a drain. The gate dielectric layer is formed on a semiconductor substrate. The floating gate is formed on the gate dielectric layer. The source and the drain are formed in the semiconductor substrate and are disposed at opposing sides of the floating gate. The coupling gate consists essentially of a capacitor dielectric layer and a contact plug, where the capacitor dielectric layer is formed on the floating gate, and the contact plug is formed on the capacitor dielectric layer. | 09-01-2011 |
| 20120091424 | NON-VOLATILE MEMORY DEVICE AND METHODS FOR MANUFACTURING THE SAME - A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification. | 04-19-2012 |
| Patent application number | Description | Published |
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| 20090278781 | TUNABLE CURRENT DRIVER AND OPERATING METHOD THEREOF - A tunable current driver comprising a semiconductor memory device and a selective transistor is provided, in which one of the source/drain pair of the semiconductor memory device is electrically coupled with a lighting device, and one of the source/drain pair of the selective transistor is electrically coupled with the gate electrode of the semiconductor memory device. The semiconductor memory device not only acts as “drive transistor” to drive the lighting device, but also is capable of adjusting the threshold voltage thereof. | 11-12-2009 |
| 20090296474 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 12-03-2009 |
| 20110116317 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 05-19-2011 |
| 20110260292 | Bipolar Junction Transistor Having a Carrier Trapping Layer - A bipolar junction transistor having a carrier trapping layer, comprises a semi-conductor substrate including a well with a first type ions formed thereon; two impurity regions with a second type ions formed opposite with each other over the well; an insulation layer over the well, and edges extend over the second two impurity regions; and a carrier trapping layer formed over the insulation layer. | 10-27-2011 |
