Patent application number | Description | Published |
20090263485 | Targeted hollow gold nanostructures and methods of use - Provided are novel nanostructures comprising hollow nanospheres and nanotubes for use as chemical sensors and molecular specific photothermal coupling agents. The nanostructures can be used in laser-induced phototherapy for treatment of cancer and other disorders. The nanostructures can also be used as a sensor that detects molecules. The nanostructures are of particular use in the fields of clinical diagnosis, clinical therapy, clinical treatment, and clinical evaluation of various diseases and disorders, manufacture of compositions for use in the treatment of various diseases and disorders, for use in molecular biology, structural biology, cell biology, molecular switches, molecular circuits, and molecular computational devices, and the manufacture thereof. The hollow gold nanospheres have a unique combination of spherical shape, small size, and strong, tunable, and narrow surface plasmon resonance absorption covering the entire visible to near IR region. | 10-22-2009 |
20110165611 | DUAL MODALITY DETECTION OF APOPTOSIS - To image apoptosis in vivo, small, membrane-permeable probes comprising a caspase 3 substrate, a fluorogenic dye and a radionuclide is provided. This dual-modality probe can be cleaved by caspase upon exposure to apoptotic cells, allowing imaging of caspase 3 and 7 activities using both optical and nuclear imaging techniques. The combined use of these methods provides the opportunity for a direct correlation between in vitro and in vivo biological activities and a viable method to treat disease | 07-07-2011 |
Patent application number | Description | Published |
20090096055 | METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH - An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width. | 04-16-2009 |
20090098702 | Method to Form CMOS Circuits Using Optimized Sidewalls - A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed. | 04-16-2009 |
20090253253 | METHOD OF ADJUSTING FDSOI THRESHOLD VOLTAGE THROUGH OXIDE CHARGES GENERATION IN THE BURIED OXIDE - Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip. | 10-08-2009 |
20100052025 | SOI MUGFETS HAVING SINGLE GATE ELECTRODE LEVEL - A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region. | 03-04-2010 |
20110070703 | Disposable Spacer Integration with Stress Memorization Technique and Silicon-Germanium - An integrated process flow for forming an NMOS transistor ( | 03-24-2011 |
20120045874 | CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT - Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (V | 02-23-2012 |
20120108027 | IMPROVED SILICIDE METHOD - A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide. | 05-03-2012 |
20120119824 | BIAS VOLTAGE SOURCE - An integrated circuit that includes a data storage cell. The data storage cell has a PMOS transistor in an n-well. In addition, the data storage cell has a PMOS diode connecting a voltage source to a bias node of the n-well. Alternatively, an integrated circuit that includes a data storage cell. The alternative data storage cell has an NMOS transistor in an isolated p-well. In addition, the alternative data storage cell has an NMOS diode connecting a voltage source to a bias node of the isolated p-well. | 05-17-2012 |
20120280324 | SRAM STRUCTURE AND PROCESS WITH IMPROVED STABILITY - An SRAM memory cell with reduced SiGe formation area using a gate extension ( | 11-08-2012 |
Patent application number | Description | Published |
20090199216 | MULTI-LEVEL DRIVER CONFIGURATION - A method, medium and implementing processing system are provided in which the Operating System (OS) driver is divided into two parts, viz. an upper level OS driver and a lower level OS driver. The lower level OS driver sets up the adapter hardware and any adapter hardware work-around. The upper level OS driver is interfaced to the OS communication stack and each can be compiled separately. The upper OS driver is compiled and shipped with the OS to make sure it is compatible with the OS communication stack. The lower OS driver, in an exemplary embodiment, is compiled and stored in an adapter flash memory. The OS dynamically combines the upper and lower OS drivers together during the load time. | 08-06-2009 |
20090300211 | REDUCING IDLE TIME DUE TO ACKNOWLEDGEMENT PACKET DELAY - Mechanisms for reducing the idle time of a computing device due to delays in transmitting/receiving acknowledgement packets are provided. A first data amount corresponding to a window size for a communication connection is determined. A second data amount, in excess of the first data amount, which may be transmitted with the first data amount, is calculated. The first and second data amounts are then transmitted from the sender to the receiver. The first data amount is provided to the receiver in a receive buffer of the receiver. The second data amount is maintained in a switch port buffer of a switch port without being provided to the receive buffer. The second data amount is transmitted from the switch port buffer to the receive buffer in response to the switch port detecting an acknowledgement packet from the receiver. | 12-03-2009 |
20100318666 | EXPEDITING ADAPTER FAILOVER - Expediting adapter failover may minimize network downtime and preserve network performance. Embodiments may comprise copying a primary adapter memory of a failing primary adapter to a standby adapter memory of a standby adapter. Copying the memory may expedite TCP/IP offload adapter failover by maintaining TCP/IP stack and connection information. In several embodiments, Copy Logic may copy primary adapter memory to standby adapter memory. In some embodiments, Detect Logic may monitor primary adapter viability and may initiate failover. In additional embodiments, Assess Logic may assess whether the IO bus is operative permitting Direct Logic to copy adapter memory via, e.g., DMA. In other embodiments, Packet Logic may fragment primary adapter memory into network packets sent through the network to the standby adapter where Unpack Logic may unpack them into memory. | 12-16-2010 |
20120203878 | Method for Changing Ethernet MTU Size on Demand with No Data Loss - A method and system for substantially avoiding loss of data and enabling continuing connection to the application during an MTU size changing operation in an active network computing device. Logic is added to the device driver, which logic provides several enhancements to the MTU size changing operation/process. Among these enhancements are: (1) logic for temporarily pausing the data coming in from the linked partner while changing the MTU size; (2) logic for returning a “device busy” status to higher-protocol transmit requests during the MTU size changing process. This second logic prevents the application from issuing new requests until the busy signal is removed; and (3) logic for enabling resumption of both flows when the MTU size change is completed. With this new logic, the device driver/adapter does not have any transmit and receive packets to process for a short period of time, while the MTU size change is ongoing. | 08-09-2012 |
Patent application number | Description | Published |
20110173708 | NOVEL GENE DISRUPTIONS, COMPOSITIONS AND METHODS RELATING THERETO - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO226, PRO257, PRO268, PRO290, PRO36006, PRO363, PRO365, PRO382, PRO444, PRO705, PRO1071, PRO1125, PRO1134, PRO1155, PRO1281, PRO1343, PRO1379, PRO1380, PRO1387, PRO1419, PRO1433, PRO1474, PRO1550, PRO1571, PRO1572, PRO1759, PRO1904, PRO35193, PRO4341, PRO4348, PRO4369, PRO4381, PRO4407, PRO4425, PRO4985, PRO4989, PRO5737, PRO5800, PRO5993, PRO6017, PRO7174, PRO9744, PRO9821, PRO9852, PRO9873, PRO10196, PRO34778, PRO20233, PRO21956, PRO57290, PRO38465, PRO38683 or PRO85161 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as neurological disorders; cardiovascular, endothelial or angiogenic disorders; eye abnormalities; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; lipid metabolic disorders; or developmental abnormalities. | 07-14-2011 |
20120272341 | NOVEL GENE DISRUPTIONS, COMPOSITIONS AND METHODS RELATING THERETO - The present invention relates to transgenic animals, as well as compositions and methods relating to the characterization of gene function. Specifically, the present invention provides transgenic mice comprising disruptions in PRO226, PRO257, PRO268, PRO290, PRO36006, PRO363, PRO365, PRO382, PRO444, PRO705, PRO1071, PRO1125, PRO1134, PRO1155, PRO1281, PRO1343, PRO1379, PRO1380, PRO1387, PRO1419, PRO1433, PRO1474, PRO1550, PRO1571, PRO1572, PRO1759, PRO1904, PRO35193, PRO4341, PRO4348, PRO4369, PRO4381, PRO4407, PRO4425, PRO4985, PRO4989, PRO5737, PRO5800, PRO5993, PRO6017, PRO7174, PRO9744, PRO9821, PRO9852, PRO9873, PRO10196, PRO34778, PRO20233, PRO21956, PRO57290, PRO38465, PRO38683 or PRO85161 genes. Such in vivo studies and characterizations may provide valuable identification and discovery of therapeutics and/or treatments useful in the prevention, amelioration or correction of diseases or dysfunctions associated with gene disruptions such as neurological disorders; cardiovascular, endothelial or angiogenic disorders; eye abnormalities; immunological disorders; oncological disorders; bone metabolic abnormalities or disorders; lipid metabolic disorders; or developmental abnormalities. | 10-25-2012 |
Patent application number | Description | Published |
20100054267 | Creating and Maintaining Traffic Engineered Database for Path Computation Element - An apparatus comprising a node configured to communicate with a path computation element (PCE) and a neighbor node, wherein the node is configured to send a local traffic engineering (TE) information directly to the PCE without sending the local TE information to the neighbor node. Also disclosed is a network component comprising at least one processor configured to implement a method comprising establishing a PCE protocol (PCEP) session with a PCE, and sending a TE information directly to the PCE without flooding the TE information. Also disclosed is a method comprising receiving a TE information, updating a first TE database (TED) using the TE information, and synchronizing the first TED with a second TED. | 03-04-2010 |
20110064086 | Fiber Channel over Ethernet and Fiber Channel Switching Based on Ethernet Switch Fabrics - An apparatus comprising a Converged Port Controller (CPC) comprising a plurality of first ports and a plurality of second ports, and an Ethernet Switch Fabric (ESF) coupled to the second ports, wherein the CPC is configured to receive a plurality of Fiber Channel over Ethernet (FCoE) frames on the first ports, modify at least some of the FCoE frames, thereby producing modified FCoE frames, and transmit the FCoE frames on the second ports. An apparatus comprising at least one processor configured to implement a method comprising receiving a plurality of FCoE frames, a plurality of Fiber Channel (FC) frames, and a plurality of Ethernet frames, modifying the FCoE frames, thereby producing modified FCoE frames, encapsulating the FC frames in an Ethernet format, thereby producing a plurality of second FCoE frames, and switching the modified FCoE frames, the second FCoE frames, and the Ethernet frames using an Ethernet switch fabric. | 03-17-2011 |
20110228782 | Method for Performing Protocol Translation in a Network Switch - A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet. | 09-22-2011 |
20120014386 | Delegate Gateways and Proxy for Target Hosts in Large Layer 2 and Address Resolution with Duplicated Internet Protocol Addresses - An apparatus comprising a plurality of district boundary bridges (DBBs) in a plurality of second network districts configured to couple to a plurality of core bridges in a core network district and to a plurality of end-stations in the second network districts via a plurality of intermediate switches in the second network districts; wherein the core bridges and the DBBs are aware of a plurality of Media Access Control (MAC) addresses of the DBBs but are not aware of Internet Protocol (IP) addresses and MAC addresses of the end-stations, and wherein the IP addresses of the end-stations are mapped in a directory service (DS) in the core network district to the MAC addresses of the corresponding DBBs in the corresponding second network districts of the end-stations. | 01-19-2012 |
20120275301 | Port and Priority Based Flow Control Mechanism for Lossless Ethernet - An apparatus comprising an aggregation/core switch configure to couple to an edge switch and receive information about a plurality of end system facing ports of the edge switch, wherein the information about the end system facing ports is used to associate the end system facing ports with a plurality of corresponding queues at the aggregation/core switch. Also disclosed is a network component comprising a receiver configured to receive information about a plurality of end system facing ports of an edge switch, a processor configured to establish and associate the end system facing ports with a plurality of corresponding queues, and a transmitter configured to return information about the associated end system facing ports. | 11-01-2012 |
20120275339 | Method and System of Centralized Control and Management for Fiber Channel Over Ethernet Networks - A method implemented in an FCoE controller and manager (FCM) coupled to a first fiber channel over Ethernet (FCoE) data forwarder (FDF), the method comprising sending to the first FDF a first Controlling FDF Information (CFI) request that requests the name of the first FDF, receiving from the first FDF a first CFI acceptance comprising the name of the first FDF, receiving from the first the second CFI acceptance associated with a second FDF, wherein the first CFI acceptance and the second CFI acceptance allow the FCM to develop topology information for a FCoE network comprising the FCM, the first FDF, and the second FDF, creating a first base forwarding table for the first FDF, and creating a second base forwarding table for the second FDF, wherein the second base forwarding table is different than the first base forwarding table. | 11-01-2012 |
20120275467 | Method and System of Centralized Control and Management for Fiber Channel Over Ethernet Networks - A first fiber channel over Ethernet (FCoE) data forwarder (FDF), comprising a memory coupled to a processor, wherein the memory comprises instructions that cause the processor to receive a base forwarding table from an FCoE controller and manager (FCM), wherein the FDF comprise a plurality of ports, and wherein the first FDF uses the base forwarding table to determine which of the ports to send a first FCoE data frame comprising fiber channel (FC) data, receive a second FCoE data frame comprising a media access control (MAC) address, a port identifier, and FC data, and update the base forwarding table using the MAC address and the port identifier. | 11-01-2012 |
20120275787 | Method and System of Centralized Control and Management for Fiber Channel Over Ethernet Networks - A fiber channel over Ethernet (FCoE) network component, comprising a first FCoE data forwarder (FDF) configured to couple to a second FDF and to a third FDF, wherein the first FDF is configured to receive a FCoE frame from the second FDF and send the FCoE frame to the third FDF, wherein the frame comprises a destination address and a fiber channel (FC) payload, and wherein the first FDF does not change the destination address of the frame when the first FDF forwards the frame to the third FDF. | 11-01-2012 |
20130148663 | Method to Carry FCoE Frames Over A TRILL Based Network - An apparatus for forwarding an Fiber Channel over Ethernet (FCoE) data frame into an Ethernet network comprising a processor configured to receive a data frame on a input port, obtain a first destination address and a virtual local area network identifier (VID), determine whether the first destination address and the VID matches an entry within a forwarding table, construct a key when the first destination address and VID matches the entry and the data frame is a FCoE frame, and forward the data frame as an outgoing data frame via an output port when the key matches a rule that permits forwarding the data frame. | 06-13-2013 |
20140301407 | METHOD FOR PERFORMING PROTOCOL TRANSLATION IN A NETWORK SWITCH - A system and method are disclosed for processing a packet. Processing the packet comprises receiving the packet; translating the packet from a first protocol-specific format to a canonical packet format; translating the packet from the canonical packet format to a second protocol-specific format; and forwarding the packet. | 10-09-2014 |
Patent application number | Description | Published |
20090031191 | Wyner-Ziv Coding Based on TCQ and LDPC Codes - An encoder employs a trellis coded quantization (TCQ) unit and a compression unit. The TCQ uses a set of polynomials that have been selected to maximize granular gain. The TCQ unit operates on a block of samples from a source. The compression unit compresses bit planes of the TCQ output, using parity check matrices of corresponding LDPC codes, to obtain corresponding syndromes. The parity check matrices are selected so their compression performance approaches close to the limit for Slepian-Wolf coding. A decoder employs a decoding unit and an estimation unit. The decoding unit decodes the syndromes using side information to produce an estimate for the TCQ output. The side information is correlated with the source. The estimation unit estimates the block of source samples using the estimated TCQ output and the side information. Trellis coded vector quantization may be used as an alternative to TCQ. | 01-29-2009 |
20090232242 | Nested Turbo Code Design for the Costa Problem - A method for the Costa problem includes turbo-like nested code. In one embodiment, the method includes providing a turbo-like trellis-coded quantization for source coding. The method also includes providing a turbo trellis-coded modulation for channel coding. | 09-17-2009 |
20110029846 | MULTI-SOURCE DATA ENCODING, TRANSMISSION AND DECODING USING SLEPIAN-WOLF CODES BASED ON CHANNEL CODE PARTITIONING - System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordance with a rate allocation among the plurality of correlated data sources. A corresponding plurality of parity matrices are generated based respectively on the sub-matrices, where each parity matrix is useable to encode data from a respective one of the correlated data sources. | 02-03-2011 |
20110161776 | COMPRESS-FORWARD CODING WITH N-PSK MODULATION FOR THE HALF-DUPLEX GAUSSIAN RELAY CHANNEL - Systems and methods that implement compress-forward (CF) coding with N-PSK modulation for the relay channel are disclosed, where N is greater than or equal to two. In the CF scheme, Wyner-Ziv coding is applied at the relay to exploit the joint statistics between signals at the relay and the destination. Quantizer design and selection of channel code parameters are discussed. Low-density parity check (LDPC) codes are used for error protection at the source, and nested scalar quantization (NSQ) and irregular repeat accumulate (IRA) codes for Wyner Ziv coding (or more precisely, distributed joint source-channel coding) at the relay. The destination system decodes original message information using (a) a first signal received from the source in a first interval and (b) a second signal that represents a mixture of transmissions from the source and relay in the second interval. | 06-30-2011 |
20110311003 | SOURCE-CHANNEL APPROACH TO CHANNEL CODING WITH SIDE INFORMATION - Code designs for channel coding with side information (CCSI) based on combined source-channel coding are disclosed. These code designs combine trellis-coded quantization (TCQ) with irregular repeat accumulate (IRA) codes. The EXIT chart technique is used for IRA channel code design (and especially for capacity-approaching IRA channel code design). We emphasize the role of strong source coding and endeavor to achieve as much granular gain as possible by using TCQ. These code designs synergistically combine TCQ with IRA codes. By bringing together TCQ and EXIT chart-based IRA code designs, we are able to approach the theoretical limit of dirty-paper coding. | 12-22-2011 |