Patent application number | Description | Published |
20100324112 | Genetic changes in ATM and ATR/CHEK1 as prognostic indicators in cancer - The present invention relates to the discovery that, in human cancer, an 11q deletion of ATM together with an increase in ATR and CHEK1 expression correlates with resistance to ionizing radiation which could be overcome by inhibition of the ATR/CHEK1 pathway. It provides for methods of identifying patients unlikely to exhibit an adequate response to radiation therapy and/or chemotherapy who may benefit from ATR/CHEK1 pathway inhibition, as well as methods of treating said patients. | 12-23-2010 |
20120295951 | GENETIC CHANGES IN ATM AND ATR/CHEK1 AS PROGNOSTIC INDICATORS IN CANCER - The present invention relates to the discovery that, in human cancer, an 11q deletion of ATM together with an increase in ATR and CHEK1 expression correlates with resistance to ionizing radiation which could be overcome by inhibition of the ATR/CHEK1 pathway. It provides for methods of identifying patients unlikely to exhibit an adequate response to radiation therapy and/or chemotherapy who may benefit from ATR/CHEK1 pathway inhibition, as well as methods of treating said patients. | 11-22-2012 |
20130338212 | Genetic Changes In ATM And ATR/Chek1 As Prognostic Indicators In Cancer - The present invention relates to the discovery that, in human cancer, an 11q deletion of ATM together with an increase in ATR and CHEK1 expression correlates with resistance to ionizing radiation which could be overcome by inhibition of the ATR/CHEK1 pathway. It provides for methods of identifying patients unlikely to exhibit an adequate response to radiation therapy and/or chemotherapy who may benefit from ATR/CHEK1 pathway inhibition, as well as methods of treating said patients. | 12-19-2013 |
Patent application number | Description | Published |
20100085352 | PARALLEL SURFACE RECONSTRUCTION - Described is a technology in which point cloud surface reconstruction is performed via parallel processing on a graphics processing unit, achieving real-time reconstruction rates. An octree is built for a given set of oriented points, with each node containing a set of points enclosed by the node. The data structure is built on the GPU, in parallel, using level-order traversals to process nodes at a same tree level. The surface is reconstructed based on data configured and located via the traversals. To produce the surface, an implicit function over the volume spanned by the octree nodes is computed using the GPU, e.g., based on a Poisson surface reconstruction method. A sparse linear system is built and a multi-grid solver is employed to solve the system. An adaptive marching cubes procedure is performed on the GPU to extract an isosurface of the implicit function as a triangular mesh | 04-08-2010 |
20100085353 | USER-GUIDED SURFACE RECONSTRUCTION - Described is a technology by which a user interacts with a surface representative of a point cloud data to correct for imperfect scan data. The surface is reconstructed based on the interaction. Real time viewing of the image is facilitated by parallel surface reconstruction. For example, the user may draw strokes to reduce topological ambiguities in poorly-sampled areas. An algorithm automatically adds new oriented sample points to the original point cloud based on the user interaction. Then a new isosurface is generated for the augmented point cloud. The user also may specify the geometry of missing areas of the surface. The user copies a set of points from another point cloud, and places the points around the target area. A new isosurface is then generated. | 04-08-2010 |
20160071224 | Smart Table Service - The instant application discloses, among other things, a Smart Table Service. In one embodiment, it may include ways for any entity, such as a restaurant, for example, to provide services to patrons, who may use their own devices. For instance, a restaurant may provide a linear barcode or quick response (QR) barcode, or other machine-readable symbol associated with a table, bar seat, or other location where a patron may wish to order, pay, call wait staff, or request other services. A patron at a location may scan a provided code using any device such as a smartphone, smartwatch, or intelligent eyewear, for example, and a server may receive a message indicating the location. In response to the location, the server may provide a web site or communicate with an app on the patron's device, allowing the patron to perform an action, such as ordering or paying. | 03-10-2016 |
Patent application number | Description | Published |
20080303840 | Mesh Quilting for Geometric Texture Synthesis - Mesh quilting for geometric texture synthesis involves synthesizing a geometric texture by quilting a mesh texture swatch. In an example embodiment, geometry is matched between a mesh texture swatch and a portion of a synthesized geometric texture. Correspondences are ascertained between elements of the mesh texture swatch and the portion of the synthesized geometric texture. The ascertained corresponding elements of the mesh texture swatch and the portion of the synthesized geometric texture are aligned via local deformation to create a new patch. The new patch is merged into an output texture space to grow the synthesized geometric texture. | 12-11-2008 |
20080316202 | DIRECT MANIPULATION OF SUBDIVISION SURFACES USING A GRAPHICS PROCESSING UNIT - A graphics system allows for manipulation of a detail mesh for a subdivision surface. To deform the subdivision surface, the graphics system generates a corresponding deformed control mesh by attempting to satisfy both position constraints of the manipulation and Laplacian constraints for the detail mesh. After the deformed control mesh is generated, the deformed detail mesh can be generated by applying a subdivision function to the deformed control mesh to generate a deformed smooth mesh and then applying detail information to the deformed smooth mesh. | 12-25-2008 |
20090063623 | DETERMINING CONNECTION INFORMATION TO USE TO ACCESS AN ARTIFACT FROM AN APPLICATION ON A REMOTE SERVER - Provided are a method, system, and article of manufacture for determining connection information to use to access an artifact from an application on a remote server. A request is received in a local server for an artifact at a target application executing on a remote server. A determination is made as to whether a local repository includes connection information on the remote server. The connection information is used to communicate the request for the artifact to the remote server over a network. The connection information is accessed from the local repository in response to determining that the local repository includes the connection information for the remote server. A determination is made as to whether a common repository is available to provide the connection information for the remote server in response to determining that the local repository does not include the connection information for the remote server. Communication is made to the common repository over the network to access the connection information for the remote server in response to determining that the common repository is available to provide the connection information. | 03-05-2009 |
20120071515 | NITROPYRIDINYL ETHYLENEIMINE COMPOUND, THE PHARMACEUTICAL COMPOSITION CONTAINING IT, THE PREPARATION METHOD AND USE THEREOF - The present invention discloses a nitropyridinyl ethyleneimine compound as shown in the formula I and a preparation method of the same, as well as use of the compound in manufacture of a prodrug and in manufacture of a drug for treating a tumor. | 03-22-2012 |
20120168770 | HEAT DISSIPATION STRUCTURE OF CHIP - A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior. | 07-05-2012 |
20120188821 | METHOD FOR ACHIEVING FOUR-BIT STORAGE USING FLASH MEMORY HAVING SPLITTING TRENCH GATE - The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased. | 07-26-2012 |
20120302014 | METHOD FOR FABRICATING SURROUNDING-GATE SILICON NANOWIRE TRANSISTOR WITH AIR SIDEWALLS - A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit. | 11-29-2012 |
20120302027 | Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching - Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle. | 11-29-2012 |
20120313154 | MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same - The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value. | 12-13-2012 |
20130001655 | Heat Dissipation Structure of SOI Field Effect Transistor - The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink. | 01-03-2013 |
20130011980 | FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR - The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased. | 01-10-2013 |
20130017654 | FABRICATION METHOD FOR SURROUNDING GATE SILICON NANOWIRE TRANSISTOR WITH AIR AS SPACERSAANM Huang; RuAACI BeijingAACO CNAAGP Huang; Ru Beijing CNAANM Zhuge; JingAACI BeijingAACO CNAAGP Zhuge; Jing Beijing CNAANM Fan; JiewenAACI BeijingAACO CNAAGP Fan; Jiewen Beijing CNAANM Ai; YujieAACI BeijingAACO CNAAGP Ai; Yujie Beijing CNAANM Wang; RunshengAACI BeijingAACO CNAAGP Wang; Runsheng Beijing CNAANM Huang; XinAACI BeijingAACO CNAAGP Huang; Xin Beijing CN - The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO | 01-17-2013 |
20140073796 | NITROPYRIDINYL ETHYLENEIMINE COMPOUND, THE PHARMACEUTICAL COMPOSITION CONTAINING IT, THE PREPARATION METHOD AND USE THEREOF - The present invention discloses a nitropyridinyl ethyleneimine compound as shown in the formula I and a preparation method of the same, as well as use of the compound in manufacture of a prodrug and in manufacture of a drug for treating a tumor. | 03-13-2014 |
Patent application number | Description | Published |
20090054553 | HIGH DIELECTRIC CONSTANT THERMOPLASTIC COMPOSITION, METHODS OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME - Disclosed herein is a composition comprising a thermoplastic polymer; about 10 to about 60 weight percent of a dielectric filler having a dielectric constant greater than or equal to about 25 when measured at 900 megahertz; and about 1 to about 10 weight percent of a fibrous composition, the weight percent being based on the total weight of the composition. Disclosed herein too is a method comprising melt blending a composition comprising a thermoplastic polymer; about 10 to about 60 weight percent of a dielectric filler having a dielectric constant greater than or equal to about 25 when measured at 900 megahertz; and about 1 to about 10 weight percent of a fibrous composition, the weight percent being based on the total weight of the composition. | 02-26-2009 |
20110148427 | TRIBOCHARGE TEST FIXTURE - A fixture can include a test fixture that holds an object whose electrostatic charge characteristics are to be measured, means for moving a piece of rubbing material into contact with the object, and means for rubbing a surface of the object. A method for measuring the electrostatic charge characteristics of an object using a test fixture can include: placing the object in the test fixture, moving a piece of rubbing material into contact with the object and rubbing a surface of the object with the piece of rubbing material for a period of time. The rubbing causes an electrostatic charge to be built up on the surface of the object. The electrostatic charge characteristics of the object can be measured and the measured electrostatic charge characteristics of the object can be displayed. | 06-23-2011 |
20110207498 | Resource Configuration Method, Device, and System - A resource configuration method includes acquiring capability information of a base station (BS), in which the capability information of the BS includes information indicating whether the BS has channel power boost capability. Capability information of a user equipment (UE) is acquired. The capability information of the UE includes information indicating whether the UE has the channel power boost capability. The BS is notified to configure resources for performing channel estimation by using the channel power boost capability for the UE if the UE and the BS both have the channel power boost capability. | 08-25-2011 |
20120094704 | Method, Device, and System of Resource Configuration - A method and a communications system are provided. The system includes a Node B and a RNC. The Node B report the RNC whether the base station an E-DPCCH power boost capability. The RNC is also informed whether a UE supports and E-DPCCH power boost capability. If the Node B and the UE both support the E-DPCCH power boost capability, the RNC configures the resource for the Node B to perform channel estimation by using the E-DPCCH power boost feature for the UE. Through the solution of the system, the accuracy of channel estimation can be improved and thus a bit error rate in high-speed data transmission can be reduced. | 04-19-2012 |
20120201121 | HIGH SPEED UPLINK PACKET ACCESS ADAPTIVE RETRANSMISSION METHOD AND APPARATUS - An embodiment of the present invention discloses a high speed uplink packet access adaptive retransmission method and apparatus. The method includes: obtaining a resource limitation state; performing adjustment decision according to the resource limitation state and a current target number of retransmissions of a UE; and adjusting the target number of retransmissions of the UE between a preset large target number of retransmissions and a preset small target number of retransmissions, where the large target number of retransmissions is greater than the small target number of retransmissions. The utilization rate of resources may be effectively improved. | 08-09-2012 |
20130070709 | Method, Device, and System of Resource Configuration - A method and a communications system are provided. The system includes a base station and a RNC. The base station does not report the RNC whether the base station supports an E-DPCCH power boost capability. The RNC is also informed whether a UE supports and E-DPCCH power boost capability. If the UE supports E-DPCCH power boost function, the RCE designates by default that the base station also supports the E-DPCCH power boost function even though the base station does not report whether it supports or not, and configures resources for the base station to perform channel estimation by using the E-DPCCH power boost feature for the UE. Through the solution of the system, the accuracy of channel estimation can be improved and thus a bit error rate in high-speed data transmission can be reduced. | 03-21-2013 |
20140269580 | METHOD AND APPARATUS FOR DETERMINING POWER OFFSET PARAMETERS - The present invention discloses a method and an apparatus for determining a power offset parameter. The method for determining the power offset parameter provided in the present invention comprises: obtaining data throughput rate and/or cell resource usage state of a terminal; determining a resource state of the terminal according to the data throughput rate and/or the cell resource usage state and a corresponding threshold; determining power offset parameter configuration corresponding to the resource state according to the determined resource state; and sending the power offset parameter configuration to the terminal, so that the terminal determines the power offset parameter according to the power offset parameter configuration. | 09-18-2014 |
20140334327 | METHOD, APPARATUS, AND SYSTEM FOR ADJUSTING CQI FEEDBACK CYCLE - Embodiments of the present invention disclose a method, an apparatus, and a system for adjusting a channel quality indicator CQI feedback cycle. A CQI adjustment parameter fed back by a base station is received, and it is determined according to the CQI adjustment parameter whether a CQI feedback cycle of a user equipment needs to be adjusted; and when it is determined that the CQI feedback cycle needs to be adjusted, the CQI feedback cycle of the user equipment is adjusted, and an adjusted CQI feedback cycle is sent to the user equipment. Therefore, the CQI feedback cycle of the user equipment is dynamically adjusted, and an uplink throughput rate and cell uplink coverage are increased. | 11-13-2014 |
20150131575 | METHOD, DEVICE, AND SYSTEM FOR RESOURCE CONFIGURATION - A method and a communications system are provided. The system includes a base station and a RNC. The base station does not report the RNC whether the base station supports an E-DPCCH power boost capability. The RNC is also informed whether a UE supports and E-DPCCH power boost capability. If the UE supports E-DPCCH power boost function, the RCE designates by default that the base station also supports the E-DPCCH power boost function even though the base station does not report whether it supports or not, and configures resources for the base station to perform channel estimation by using the E-DPCCH power boost feature for the UE. If the base station itself does not support E-DPCCH power boost capability, the base station configures its resources accordingly and performs the channel estimation by using DPCCH. | 05-14-2015 |