Patent application number | Description | Published |
20120254699 | DYNAMIC READ CHANNEL CALIBRATION FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level. | 10-04-2012 |
20130007344 | Apparatus, System, and Method for Refreshing Non-volatile Memory - Described herein are an apparatus, system, and method for refreshing a non-volatile memory. The method comprises loading a time stamp, corresponding to data in a data location of a non-volatile memory, to a register; determining an elapsed time, corresponding to the data in the data location, according to the loaded time stamp; and refreshing data of the data location for which it is determined that the elapsed time exceeds a refresh time associated with the non-volatile memory. | 01-03-2013 |
20130073786 | APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NON-VOLATILE MEMORY - Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB. | 03-21-2013 |
20130268726 | Dual Mode Write Non-Volatile Memory System - Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments. | 10-10-2013 |
20130343129 | EXTENDED SELECT GATE LIFETIME - A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command. | 12-26-2013 |
20140006847 | Defect Management in Memory Systems | 01-02-2014 |
20140047302 | CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY - Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. | 02-13-2014 |
20140089563 | CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS - According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device. | 03-27-2014 |
20140164863 | ADAPTIVE MOVING READ REFERENCES FOR MEMORY CELLS - Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a non-volatile memory included in a storage device. Priorities may be adaptively assigned to entries included in the MRR table and the entries may be ordered for use based on the assigned priorities. Other examples are described and claimed. | 06-12-2014 |
20140164872 | ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL MEMORY - Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data. | 06-12-2014 |
20140173174 | LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY - An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used. | 06-19-2014 |
20140281813 | DATA INTEGRITY MANAGEMENT IN MEMORY SYSTEMS - Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data. | 09-18-2014 |
20140297924 | NONVOLATILE MEMORY ERASURE TECHNIQUES - Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed. | 10-02-2014 |
20140307507 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 10-16-2014 |
20150019922 | Techniques for Adaptive Moving Read References for Memory Cell Read Error Recovery - Examples are given for generating or providing a moving read reference (MRR) table for recovering from a read error of non-volatile memory included in a storage device. In some examples, priorities may be adaptively assigned to entries included in the MRR table. The entries may be ordered for use based on the assigned priorities. In other examples, the MRR table may be ordered for use such that entries with a single MRR value for each read reference value may be used first over entries having multiple MRR values for each read reference value. For these other examples, the MRR table may be adaptively reordered based on which entries were successful or unsuccessful in recovering from a read error but may still be arranged to have single MRR value entries used first for use to recover from another read error. | 01-15-2015 |
20150026386 | Erase Management in Memory Systems - Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system. | 01-22-2015 |
20150078088 | EXTENDED SELECT GATE LIFETIME - A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range. | 03-19-2015 |