Patent application number | Description | Published |
20090287619 | Differentiated, Integrated and Individualized Education - A computer-based learning system uses knowledge points organized with a predefined multilevel arrangement. Each knowledge point has an information set which may include a knowledge content, an evaluation content and a solution content. For a given knowledge point, the learning system provides the knowledge content and evaluation content, analyzes the user's answers to the evaluation content and determines the next knowledge point to be studied by the user based on the user's answers and the predefined multilevel arrangement of the knowledge points. The learning system thus provides a different learning course for different users to achieve individualized learning. User's learning history may be recorded to facilitate reviews by the user and improve the selection of the next knowledge point. Users may provide feedbacks on knowledge contents and evaluation contents, and may even suggest their own knowledge contents and evaluation contents to improve the learning system and user participation. | 11-19-2009 |
20100129783 | Self-Adaptive Study Evaluation - A study evaluation system used for computer-based learning uses evaluation contents arranged in a multilevel arrangement for self-adaptive study evaluation. The study evaluation system provides a present evaluation content to a user through user interaction, and determines a subsequent evaluation content or a subsequent knowledge point to be studied by the user at least partially based on the user feedback on the present evaluation content, the multilevel arrangement of the evaluation contents, and a characteristic information of the user. The study evaluation system may further establish a data set for each user to record the user feedbacks on the evaluation contents, and use the data set in combination with certain basic user information to realize individualized study evaluation. | 05-27-2010 |
20120215990 | METHOD AND APPARATUS FOR SELECTING A NODE WHERE A SHARED MEMORY IS LOCATED IN A MULTI-NODE COMPUTING SYSTEM - A method and an apparatus for selecting a node where a shared memory is located in a multi-node computing system are provided, improving the total access performance of the multi-node computing system. The method comprises: acquiring parameters for determining a sum of memory affinity weight values between each of the CPUs and a memory on a random one of nodes; calculating the sum of the memory affinity weight values between each of the CPUs and the memory on the random one of the nodes according to the parameters; and selecting the node with the calculated minimal sum of the memory affinity weight values as the node where the shared memory for each of the CPUs is located. | 08-23-2012 |
20120272022 | DATA ACCESS PROCESSING METHOD AND APPARATUS - A data access processing method and apparatus, the method comprising: copying a kernel code and a global descriptor table on a memory of each of nodes respectively ( | 10-25-2012 |
20120272029 | MEMORY ACCESS MONITORING METHOD AND DEVICE - A memory access monitoring method and a memory access monitoring method device are disclosed, The method comprises: performing coarse grain monitoring on local memory pages, if a hot page with coarse grain monitoring exists in the local memory pages, requesting an operating system to perform an optimized migration for the content of the hot page, and if a half hot page with coarse grain monitoring exists in the local memory pages, initiating fine grain monitoring to the half hot page; and performing fine grain monitoring on the half hot page, if a hot area with fine grain monitoring exists in the half hot page, requesting the operating system to perform an optimized migration for the content of the hot area. | 10-25-2012 |
20120297149 | METHOD AND DEVICE FOR MULTITHREAD TO ACCESS MULTIPLE COPIES - A method and a device for multithread to access multiple copies. The method includes: when multiple threads of a process are distributed to different nodes, creating a thread page directory table whose content is the same as that of a process page directory table of the process, where each thread page directory table includes a special entry which points to specific data and a common entry other than the special entry, each thread corresponds to a thread page directory table, and the specific data is data with multiple copies at different nodes; and when each thread is scheduled and the special entry in the thread page directory table of the each thread does not point to the specific data stored in a node where the thread is located, modifying, based on a physical address of the specific data, the special entry to point to the specific data. | 11-22-2012 |
20130046910 | METHOD FOR MANAGING A PROCESSOR, LOCK CONTENTION MANAGEMENT APPARATUS, AND COMPUTER SYSTEM - A method for managing a processor includes: obtaining an online request of a processor of a computer system; collecting lock contention information of the computer system if a lock contention status flag indicates a non-lock thrashing status; determining whether the computer system is in a lock thrashing status according to the lock contention information; and accepting the online request if it is determined that the computer system is in a non-lock thrashing status. By using the management method according to embodiments of the present application, processor performance degradation and a waste of idle processor resources that are caused by the case that the computer system is in a lock thrashing status are prevented, thereby improving utilization efficiency of processor resources and promoting overall performance of the computer system. | 02-21-2013 |
20130054764 | Registration Method of CIM Provider in CIM System and CIMOM - A registration method includes acquiring, by a second CIMOM, parameters of a CIM provider from a first CIMOM by using information of a namespace to which a device to be configured belongs or device information of the device to be configured. The second CIMOM obtains identification information of the CIM provider in the parameters of the CIM provider through matching according to the device information or model information of the device to be configured. The second CIMOM acquires the CIM provider from the first CIMOM by using the obtained identification information of the CIM provider, and registering the CIM provider. | 02-28-2013 |
20130151747 | CO-PROCESSING ACCELERATION METHOD, APPARATUS, AND SYSTEM - An embodiment of the present invention discloses a co-processing acceleration method, including: receiving a co-processing request message which is sent by a compute node in a computer system and carries address information of to-be-processed data; according to the co-processing request message, obtaining the to-be-processed data, and storing the to-be-processed data in a public buffer card; and allocating the to-be-processed data stored in the public buffer card to an idle co-processor card in the computer system for processing. An added public buffer card is used as a public data buffer channel between a hard disk and each co-processor card of a computer system, and to-be-processed data does not need to be transferred by a memory of the compute node, which avoids overheads of the data in transmission through the memory of the compute node, and thereby breaks through a bottleneck of memory delay and bandwidth, and increases a co-processing speed. | 06-13-2013 |
20140250248 | METHOD FOR MANAGING A PROCESSOR, LOCK CONTENTION MANAGEMENT APPARATUS, AND COMPUTER SYSTEM - A method for managing a processor includes: obtaining an online request of a processor of a computer system; collecting lock contention information of the computer system if a lock contention status flag indicates a non-lock thrashing status; determining whether the computer system is in a lock thrashing status according to the lock contention information; and accepting the online request if it is determined that the computer system is in a non-lock thrashing status. By using the management method according to embodiments of the present application, processor performance degradation and a waste of idle processor resources that are caused by the case that the computer system is in a lock thrashing status are prevented, thereby improving utilization efficiency of processor resources and promoting overall performance of the computer system. | 09-04-2014 |