Patent application number | Description | Published |
20080217663 | Enhanced Transistor Performance by Non-Conformal Stressed Layers - NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching. | 09-11-2008 |
20080224118 | HEAT-SHIELDED LOW POWER PCM-BASED REPROGRAMMABLE EFUSE DEVICE - An electrically re-programmable fuse (eFUSE) device for use in integrated circuit devices includes an elongated heater element, an electrically insulating liner surrounding an outer surface of the elongated heater element, corresponding to a longitudinal axis thereof, leaving opposing ends of the elongated heater element in electrical contact with first and second heater electrodes. A phase change material (PCM) surrounds a portion of an outer surface of the electrically insulating liner, a thermally and electrically insulating layer surrounds an outer surface of the PCM, with first and second fuse electrodes in electrical contact with opposing ends of the PCM. The PCM is encapsulated within the electrically insulating liner, the thermally and electrically insulating layer, and the first and second fuse electrodes. | 09-18-2008 |
20080251284 | Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme - An electronic structure including a substrate having a having a dielectric layer with at least one metallic interconnect structure within and a dielectric barrier layer above the dielectric layer, and a multi-layer hardmask stack coated with a self-assembled layer, where the self-assembled layer is a pattern of nanoscale and/or microscale voids which are generated into the dielectric barrier layer and into the dielectric layer next to the metallic interconnect structure to create columns in the dielectric barrier layer and dielectric layer therein. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. | 10-16-2008 |
20080277765 | INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT. | 11-13-2008 |
20090169886 | NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION - Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods. | 07-02-2009 |
20100012950 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop. | 01-21-2010 |
20100013043 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate. | 01-21-2010 |
20100073997 | PIEZO-DRIVEN NON-VOLATILE MEMORY CELL WITH HYSTERETIC RESISTANCE - A piezoelectrically programmed, non-volatile memory cell structure includes a programmable piezo-resistive hysteretic material (PRHM) that is capable of being interconverted between a low resistance state and high resistance state through applied pressure cycling thereto; a piezoelectric material mechanically coupled to the PHRM such that an applied voltage across the piezoelectric material results in one of a tensile or compressive stress applied to the PRHM, depending upon the polarity of the applied voltage; and one or more electrodes in electrical communication with the PRHM, wherein the one or more electrodes are configured to provide a write programming current path through the piezoelectric material and a read current path through the PRHM. | 03-25-2010 |
20100081259 | DISLOCATION ENGINEERING USING A SCANNED LASER - A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions. | 04-01-2010 |
20110012176 | Multiple Orientation Nanowires With Gate Stack Stressors - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 01-20-2011 |
20110012177 | Nanostructure For Changing Electric Mobility - A structure and a method for a semiconductor including a nanostructure semiconductor channel. The semiconductor may include a dielectric and an electrode, the electrode attached to the dielectric, a semiconductor channel may be disposed proximate to the dielectric, wherein the semiconductor channel has an electric mobility and is configured to have at least one dimension, and wherein the dielectric may be configured to apply a force at the at least one dimension. | 01-20-2011 |
20110140245 | STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES - A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT. | 06-16-2011 |
20110207286 | Reprogrammable Fuse Structure and Method - A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry. | 08-25-2011 |
20120121906 | NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION - Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods. | 05-17-2012 |
20120294322 | Dislocation Engineering Using a Scanned Laser - A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam. | 11-22-2012 |
20120322215 | COMMUNICATION - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 12-20-2012 |
20130015507 | MULTIPLE ORIENTATION NANOWIRES WITH GATE STACK SENSORS - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t | 01-17-2013 |
20130075913 | STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. | 03-28-2013 |
20130171817 | STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. | 07-04-2013 |
20140154872 | DISLOCATION ENGINEERING USING A SCANNED LASER - A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions. | 06-05-2014 |
20140154873 | DISLOCATION ENGINEERING USING A SCANNED LASER - A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam. | 06-05-2014 |
20140302685 | DIELETRIC CAP HAVING MATERIAL WITH OPTICAL BAND GAP TO SUBSTANTIALLY BLOCK UV RADIATION DURING CURING TREATMENT, AND RELATED METHODS - A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability. | 10-09-2014 |
20140312467 | THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES - Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining. | 10-23-2014 |
20140312502 | THROUGH-VIAS FOR WIRING LAYERS OF SEMICONDUCTOR DEVICES - Through-via structures and methods of their formation are disclosed. In one such method, a first etch through at least a first dielectric material of a wiring layer is performed such that a first hole outlining a collar structure for the through-via is formed. In addition, a stress-abating dielectric material is deposited in the hole such that the stress-abating dielectric material is disposed at least laterally from the first dielectric material. Further, a second etching through at least a semiconductor material of a semiconductor layer that is disposed below the wiring layer is performed, where the second etching forms a via hole in the semiconductor material. Additionally, at least a portion of the via hole is filled with conductive material to form the through-via such that the stress-abating dielectric material, at least in the wiring layer, provides a buffer between the conductive material and the first dielectric material. | 10-23-2014 |