Patent application number | Description | Published |
20090130779 | Method of Forming a Magnetic Tunnel Junction Structure - In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer. | 05-21-2009 |
20090161422 | Magnetic Tunnel Junction Device with Separate Read and Write Paths - In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path. | 06-25-2009 |
20090194832 | Magnetic Tunnel Junction Cell Including Multiple Magnetic Domains - In a particular embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes an MTJ cell having multiple sidewalls that extend substantially normal to a surface of a substrate. Each of the multiple sidewalls includes a free layer to carry a unique magnetic domain. Each of the unique magnetic domains is adapted to store a digital value. | 08-06-2009 |
20090243009 | Magnetic Tunnel Junction Cell Including Multiple Vertical Magnetic Domains - Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value. | 10-01-2009 |
20090261434 | STT MRAM Magnetic Tunnel Junction Architecture and Integration - A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect for communicating with at least one control device and a first electrode for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier using a first mask. The device also includes an MTJ stack for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second metal interconnect is coupled to the second electrode and at least one other control device. | 10-22-2009 |
20090261437 | Two Mask MTJ Integration For STT MRAM - A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization. | 10-22-2009 |
20090321859 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, the method includes depositing a cap layer on a magnetic tunnel junction (MTJ) structure, depositing a first spin-on material layer over the cap layer, and etching the first spin-on material layer and at least a portion of the cap layer. | 12-31-2009 |
20090323410 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction in a region in which a substrate resides during a deposition of a first magnetic material onto the substrate. The method further includes applying a second magnetic field along a second direction in the region during the deposition of the first magnetic material onto the substrate. | 12-31-2009 |
20090327983 | Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology - A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component. | 12-31-2009 |
20100038744 | Shallow Trench Isolation - Shallow trench isolation methods are disclosed. In a particular embodiment, a method includes implanting oxygen under a bottom surface of a narrow trench of a silicon substrate and performing a high-temperature anneal of the silicon substrate to form a buried oxide layer. The method also includes performing an etch to deepen the narrow trench to reach the buried oxide layer. The method further includes depositing a filling material to form a top filling layer in the narrow trench. | 02-18-2010 |
20100057411 | PREDICTIVE MODELING OF CONTACT AND VIA MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY - A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via. | 03-04-2010 |
20100074092 | Reducing Spin Pumping Induced Damping of a Free Layer of a Memory Device - A system and method of reducing spin pumping induced damping of a free layer of a memory device is disclosed. The memory device includes an anti-ferromagnetic material (AFM) pinning layer in contact with a bit line access electrode. The memory device also includes a pinned layer in contact with the AFM pinning layer, a tunnel barrier layer in contact with the pinned layer, and a free layer in contact with the tunnel barrier layer. The memory device includes a spin torque enhancing layer in contact with the free layer and in contact with an access transistor electrode. The spin torque enhancing layer is configured to substantially reduce spin pumping induced damping of the free layer. | 03-25-2010 |
20100102404 | Magnetic Tunnel Junction and Method of Fabrication - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal. | 04-29-2010 |
20100176471 | Magnetic Element With Storage Layer Materials - According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers. | 07-15-2010 |
20100207221 | Magnetic Random Access Memory - A device includes a magnetic tunnel junction (MTJ) structure and a cap layer in contact with the MTJ structure. The device also includes a spin-on material layer in contact with a sidewall portion of the cap layer and a conducting layer in contact with at least the spin-on material layer and a portion of the MTJ structure. The cap layer has been etched to expose a portion of an electrode contact layer of the MTJ structure. The conducting layer is in electrical contact with the exposed portion of the electrode contact layer of the MTJ structure. | 08-19-2010 |
20100219491 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 09-02-2010 |
20100219493 | Method of Forming a Magnetic Tunnel Junction Device - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped. | 09-02-2010 |
20100225435 | Magnetic Film Enhanced Inductor - An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film. | 09-09-2010 |
20100258776 | Shallow Trench Type Quadri-Cell of Phase-Change Random Access Memory (PRAM) - A method of forming a phase-change random access memory (PRAM) cell and PRAM arrangement, and embodiments of phase-change random access memory (PRAM) cells and PRAM arrangements are disclosed. A phase-change random access memory (PRAM) cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) coupled to the heater resistor, and a top electrode coupled to the phase change material. An active region between the heater resistor and the phase change material is defined by a thickness of the heater resistor. | 10-14-2010 |
20100258777 | Diamond Type Quad-Resistor Cells of PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material. | 10-14-2010 |
20100258887 | Magnetic Tunnel Junction (MTJ) and Methods, and Magnetic Random Access Memory (MRAM) Employing Same - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 10-14-2010 |
20100259349 | Magnetic Film Enhanced Inductor - An integrated magnetic film enhanced transformer and a method of forming an integrated magnetic film enhanced transformer are disclosed. The integrated magnetic film enhanced transformer includes an transformer metal having a first portion and a second portion, a top metal coupled to the transformer metal, a bottom metal coupled to the transformer metal, and an isolation film disposed between the first portion and the second portion of the transformer metal. The isolation film includes a magnetic material that can enhance a magnetic flux density B of the transformer, increase an electromotive force (EMF) of the transformer, and increase a magnetic permeability of the transformer. | 10-14-2010 |
20100289098 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis. | 11-18-2010 |
20100302843 | Spin Transfer Torque - Magnetic Tunnel Junction Device and Method of Operation - A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a spin transfer torque magnetic tunnel junction (STT-MTJ) device. | 12-02-2010 |
20100315863 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 12-16-2010 |
20110044096 | Magnetic Tunnel Junction Structure - In a particular illustrative embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The bottom electrode is coupled to a bottom surface of the fixed layer and extends along at least one sidewall of the fixed layer. | 02-24-2011 |
20110049654 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer over the MTJ cap layer. The top electrode layer includes a first nitrified metal. | 03-03-2011 |
20110049656 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming a top electrode layer over an MTJ structure. The top electrode layer includes a first nitrified metal. | 03-03-2011 |
20110090732 | Magnetic Tunnel Junction Cell Adapted to Store Multiple Digital Values - A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value. | 04-21-2011 |
20110121417 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure above a bottom electrode. The method also includes forming a diffusion barrier layer above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer. | 05-26-2011 |
20110127626 | Fabrication and Integration of Devices with Top and Bottom Electrodes Including Magnetic Tunnel Junctions - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 06-02-2011 |
20110133299 | Magnetic Tunnel Junction Device - A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled. | 06-09-2011 |
20110139497 | Via Structure Integrated in Electronic Substrate - A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided. | 06-16-2011 |
20110141796 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer. | 06-16-2011 |
20110175181 | Magnetic Tunnel Junction (MTJ) on Planarized Electrode - A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ. | 07-21-2011 |
20110186946 | Magnetic Tunnel Junction with Domain Wall Pinning - Magnetic tunnel junctions (MTJs) are manufactured having pinning sites in a ferromagnetic layer of the MTJ. The pinning sites are created using patterns in the photomask used during patterning of the ferromagnetic layer without adding additional processes to manufacturing of the MTJs. The pinning sites create energy barriers substantially preventing a domain wall in the ferromagnetic layer from passing into fixed regions of the ferromagnetic layer. Additionally, the pinning sites substantially prevent a domain wall in the ferromagnetic layer from returning to the middle of the free region. Pinning the domain wall at the boundary of the fixed region and the free region the ferromagnetic layer improves reliability and sensitivity of the MTJ. The ferromagnetic layer may be magnetized in a direction perpendicular to the plane of the ferromagnetic layer. | 08-04-2011 |
20110229687 | Through Glass Via Manufacturing Process - Fabrication of a through glass via in a relatively thick glass substrate includes patterning a through glass via hard mask on a surface of the glass substrate. The fabrication also includes wet etching a portion of the glass substrate, through the hard mask, to create a partial through glass via. The wet etching may involve applying a vapor of an oxide etch chemical, such as HF and XeF6, or applying a wet oxide etch chemical, such as HF and XeF6. The fabrication further includes passivating the etched partial through glass via, removing bottom passivation from the partial through glass via, and repeating the etching, passivating and removing to create the through glass via. The resulting through glass via has a scalloped side wall, a vertical profile and a high aspect ratio. | 09-22-2011 |
20110229985 | Fabrication of Magnetic Tunnel Junction (MTJ) Devices with Reduced Surface Roughness for Magnetic Random Access Memory (MRAM) - Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers. | 09-22-2011 |
20110233695 | Magnetoresistive Random Access Memory (MRAM) With Integrated Magnetic Film Enhanced Circuit Elements - A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions. | 09-29-2011 |
20110233696 | Perpendicular Magnetic Tunnel Junction Structure - In a particular illustrative embodiment, a method of fabricating a semiconductor device is disclosed that includes forming a metal layer over a device substrate, forming a via in contact with the metal layer, and adding a dielectric layer above the via. The method further includes etching a portion of the dielectric layer to form a trench area, and depositing a perpendicular magnetic tunnel junction (MTJ) structure within the trench area. | 09-29-2011 |
20110234357 | Three Dimensional Inductor and Transformer Design Methodology of Glass Technology - An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path. | 09-29-2011 |
20110235391 | Reference Cell Write Operations At A Memory - A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command. | 09-29-2011 |
20110291786 | Through Via Inductor Or Transformer In A High-Resistance Substrate With Programmability - A through via inductor or transformer in a high-resistance substrate in an electronic package. In one embodiment, the package comprises a target inductor which includes a through-via formed in the substrate through which a signal passes and a tuner inductor which includes a through-via formed in the substrate such that the through-via has an independent signal passing therethrough. The direction of the signal passing through the tuner inductor can be independently controlled to adjust the total inductance of the target inductor. In another embodiment, a transformer can comprise a primary loop and a secondary loop, each of which includes a plurality of through-vias that are coupled to a plurality of conductive traces. The primary loop forms a first continuous conductive path and the secondary loop forms a second continuous conductive path. A signal passing through the primary loop can induce a signal in the secondary loop such that the induced signal is dependent on the transformer ratio. | 12-01-2011 |
20120012952 | Magnetic Storage Element Utilizing Improved Pinned Layer Stack - A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer. | 01-19-2012 |
20120032287 | MRAM Device and Integration Techniques Compatible with Logic Integration - A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps. | 02-09-2012 |
20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. | 02-09-2012 |
20120086089 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. A particular embodiment includes a magnetic tunnel junction structure above a bottom electrode. The particular embodiment further includes a portion of a diffusion barrier layer adjacent to the magnetic tunnel junction structure. A top of the magnetic tunnel junction structure is connected to a conductive layer. | 04-12-2012 |
20120087184 | Magnetic Random Access Memory (MRAM) Layout with Uniform Pattern - A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 04-12-2012 |
20120107966 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 05-03-2012 |
20120205764 | Methods of Integrated Shielding into MTJ Device for MRAM - Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via. | 08-16-2012 |
20120218805 | Configurable Memory Array - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 08-30-2012 |
20120223287 | Diamond Type Quad-Resistor Cells of PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) thrilled over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material. | 09-06-2012 |
20120274436 | THROUGH VIA INDUCTOR OR TRANSFORMER IN A HIGH RESISTANCE SUBSTRATE WITH PROGRAMMABILITY - A through via inductor or transformer in a high-resistance substrate in an electronic package. The package may comprise a target inductor which includes a through-via formed in the substrate through which a signal passes and a tuner inductor which includes a through-via formed in the substrate such that the through-via has an independent signal passing therethrough. The direction of the signal passing through the tuner inductor can be independently controlled to adjust the total inductance of the target inductor. A transformer can comprise a primary loop and a secondary loop, each of which includes through-vias coupled to conductive traces. The primary loop forms a first continuous conductive path and the secondary loop forms a second continuous conductive path. A signal passing through the primary loop can induce a signal in the secondary loop such that the induced signal is dependent on the transformer ratio. | 11-01-2012 |
20130028010 | Fast MTJ Switching Write Circuit For MRAM Array - A transmission gate is arranged between a current source and a resistive memory element, a PMOS gate of the transmission gate has no source loading effect and a write current passes from the current source, and in a first direction through the resistive memory element, setting the resistive memory element to a magnetization state. An NMOS gate of the of the transmission gate has no source loading effect and another write current, passes through the resistive memory element, in a second direction opposite the first direction, and through the transmission gate, setting the resistive memory element to an opposite magnetization state. | 01-31-2013 |
20130062714 | STRAIN INDUCED REDUCTION OF SWITCHING CURRENT IN SPIN-TRANSFER TORQUE SWITCHING DEVICES - Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current. | 03-14-2013 |
20130062716 | METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure. | 03-14-2013 |
20130114336 | THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process. | 05-09-2013 |
20130119494 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 05-16-2013 |
20130119497 | MAGNETIC TUNNEL JUNCTION STRUCTURE - A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure. | 05-16-2013 |
20130121066 | CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT - A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit. | 05-16-2013 |
20130130406 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 05-23-2013 |
20130134533 | MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 05-30-2013 |
20130153854 | DIAMOND TYPE QUAD-RESISTOR CELLS OF PRAM - A method of forming a phase-change random access memory (PRAM) cell, and a structure of a phase-change random access memory (PRAM) cell are disclosed. The PRAM cell includes a bottom electrode, a heater resistor coupled to the bottom electrode, a phase change material (PCM) formed over and coupled to the heater resistor, and a top electrode coupled to the phase change material. The phase change material contacts a portion of a vertical surface of the heater resistor and a portion of a horizontal surface of the heater resistor to form an active region between the heater resistor and the phase change material. | 06-20-2013 |
20130191048 | METHOD AND DEVICE FOR ESTIMATING DAMAGE TO A MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT - A method of estimating damage to a magnetic tunnel junction (MTJ) element that includes providing an MTJ element having a magnetic barrier layer, the magnetic barrier layer having a periphery, a cross-sectional area and a thickness and comprising an inner region of undamaged magnetic barrier material and an outer region of damaged magnetic barrier material between the inner region and the periphery, determining a first value indicative of an electrical characteristic of the MTJ element, determining a second value indicative of the electrical characteristic that the MTJ element would have had if the outer region of damaged magnetic barrier material were not present and if the inner region of undamaged magnetic barrier material extended to the periphery, and calculating a value indicative of the size of the outer region of damaged magnetic barrier material from the first value and the second value. Also a computer configured to perform the method. | 07-25-2013 |
20130201757 | MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING - A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer. | 08-08-2013 |
20130235639 | MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN - A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 09-12-2013 |
20130235656 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad. | 09-12-2013 |
20130244345 | FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 09-19-2013 |
20130288395 | MAGNETIC TUNNEL JUNCTION DEVICE FABRICATION - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal. | 10-31-2013 |
20130292767 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE AND METHOD - A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular embodiment, a CMOS device includes a silicon substrate, a dielectric insulator material on the silicon substrate, and an extension layer on the dielectric insulator material. The CMOS device further includes a gate in contact with a channel and in contact with an extension region. The CMOS device also includes a source in contact with the extension region and a drain in contact with the extension region. The extension region includes a first region in contact with the source and the gate and includes a second region in contact with the drain and the gate. | 11-07-2013 |
20130293286 | TUNABLE REFERENCE CIRCUIT - A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements. | 11-07-2013 |
20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 11-07-2013 |
20130320468 | MAGNETIC ELEMENT WITH STORAGE LAYER MATERIALS - According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers. | 12-05-2013 |
20140001568 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME | 01-02-2014 |
20140010006 | NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION - A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ. | 01-09-2014 |
20140011298 | MAGNETIC TUNNEL JUNCTION STRUCTURE - A method comprises forming a trench in a substrate. The method also comprises depositing a magnetic tunnel junction (MTJ) structure within the trench. The method further comprises planarizing the MTJ. | 01-09-2014 |
20140015080 | STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION - A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device. | 01-16-2014 |
20140021570 | METHODS OF INTEGRATED SHIELDING INTO MTJ DEVICE FOR MRAM - Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via. | 01-23-2014 |
20140035075 | MAGNETIC TUNNEL JUNCTION DEVICE - A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms. | 02-06-2014 |
20140038312 | FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material. | 02-06-2014 |
20140043924 | CONFIGURABLE MEMORY ARRAY - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 02-13-2014 |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 02-20-2014 |
20140063895 | LOW COST PROGRAMMABLE MULTI-STATE DEVICE - A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure. | 03-06-2014 |
20140071739 | REFERENCE LEVEL ADJUSTMENT SCHEME - A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions (MTJs) in the reference cells can be programmed to a selected magnetic orientation using the shared write driver circuitry. The programmed reference cells can be merged with other programmed reference cells and/or with fixed reference cells to produce a tunable reference level for comparison with MTJ data cells during a read operation. Sharing write driver circuitry between data cells and reference cells allows programming of reference cells without consuming increased area on a chip or macro. | 03-13-2014 |
20140071741 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 03-13-2014 |
20140073064 | MAGNETIC TUNNEL JUNCTION (MTJ) ON PLANARIZED ELECTRODE - A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ. | 03-13-2014 |
20140147941 | MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION - A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps. | 05-29-2014 |
20140203381 | PROCESS AND APPARATUS FOR TRANSFORMING NITRIDATION/OXIDATION AT EDGES, AND PROTECTING EDGES OF MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) LAYERS - Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer. | 07-24-2014 |
20140203401 | METAL-ON-METAL (MOM) CAPACITORS HAVING LATERALLY DISPLACED LAYERS, AND RELATED SYSTEMS AND METHODS - Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor. | 07-24-2014 |
20140206104 | STRAIN INDUCED REDUCTION OF SWITCHING CURRENT IN SPIN-TRANSFER TORQUE SWITCHING DEVICES - Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current. | 07-24-2014 |
20140210021 | METHOD AND APPARATUS FOR AMELIORATING PERIPHERAL EDGE DAMAGE IN MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) DEVICE FERROMAGNETIC LAYERS - An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same. | 07-31-2014 |
20140210043 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME - One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage V | 07-31-2014 |
20140211551 | MRAM SELF-REPAIR WITH BIST LOGIC - Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array. | 07-31-2014 |
20140217532 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation. | 08-07-2014 |
20140219015 | SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL - A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage. | 08-07-2014 |
20140219016 | SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL - A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate. | 08-07-2014 |
20140231940 | STT-MRAM DESIGN ENHANCED BY SWITCHING CURRENT INDUCED MAGNETIC FIELD - A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current. | 08-21-2014 |
20140252543 | METAL-OXIDE-METAL (MOM) CAPACITOR WITH ENHANCED CAPACITANCE - A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure. | 09-11-2014 |
20140264485 | FIN-TYPE SEMICONDUCTOR DEVICE - An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin type semiconductor device comprises a fin that comprises a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The fin type semiconductor device also comprises an oxide layer. Prior to source and drain formation of the fin-type semiconductor device, a doping concentration of the oxide layer is less than the first doping concentration. | 09-18-2014 |
20140264610 | METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS - Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa. | 09-18-2014 |
20140273288 | METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure. | 09-18-2014 |
20150019147 | METHOD AND DEVICE FOR ESTIMATING DAMAGE TO MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENTS - For first and second magnetic tunnel junction (MTJ) elements, a trend in a relationship between an electrical characteristic of the first and second MTJ elements and an area of the first and second MTJ elements may be determined. Damage to a sidewall of the first and second MTJ elements may be estimated from the trend. At least one operating parameter of an MTJ manufacturing apparatus may be modified based on an X or Y intercept a trend line. | 01-15-2015 |
20150035039 | LOGIC FINFET HIGH-K/CONDUCTIVE GATE EMBEDDED MULTIPLE TIME PROGRAMMABLE FLASH MEMORY - A method for fabricating a multiple time programmable (MTP) device includes forming fins of a first conducting type on a substrate of a second conducting type. The method further includes forming a floating gate dielectric to partially surround the fins. The method also includes forming a floating gate on the floating gate dielectric. The method also includes forming a coupling film on the floating gate and forming a coupling gate on the coupling film. | 02-05-2015 |
20150036437 | FLASH MEMORY CELL WITH CAPACITIVE COUPLING BETWEEN A METAL FLOATING GATE AND A METAL CONTROL GATE - An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line. | 02-05-2015 |
20150050785 | METHOD OF FORMING A COMPLEMENTARY METAL-OXIDESEMICONDUCTOR (CMOS) DEVICE - A complementary metal-oxide-semiconductor (CMOS) device and methods of formation thereof are disclosed. In a particular example, a method of forming a CMOS device includes forming a first layer on an extension layer of a wafer, forming a first gate on a portion of the first layer, and forming an expansion region proximate to the extension layer. The method also includes removing a portion of the first gate to create a cavity and removing a portion of the first layer to extend the cavity to the extension layer. | 02-19-2015 |
20150056722 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 02-26-2015 |
20150069458 | VERTICAL TUNNEL FIELD EFFECT TRANSISTOR - A tunnel field transistor (TFET) device includes a fin structure that protrudes from a substrate surface. The fin structure includes a base portion proximate to the substrate surface, a top portion, and a first pair of sidewalls extending from the base portion to the top portion. The first pair of sidewalls has a length corresponding to a length of the fin structure. The fin structure also includes a first doped region having a first dopant concentration at the base portion of the fin structure. The fin structure also includes a second doped region having a second dopant concentration at the top portion of the fin structure. The TFET device further includes a gate including a first conductive structure neighboring a first sidewall of the first pair of sidewalls. A dielectric layer electrically isolates the first conductive structure from the first sidewall. | 03-12-2015 |