Patent application number | Description | Published |
20100307913 | PLATING APPARATUS FOR METALLIZATION ON SEMICONDUCTOR WORKPIECE - The present invention provides a plating apparatus with multiple anode zones and cathode zones. The electrolyte flow field within each zone is controlled individually with independent flow control devices. A gas bubble collector whose surface is made into pleated channels is implemented for gas removal by collecting small bubbles, coalescing them, and releasing the residual gas. A buffer zone built within the gas bubble collector further allows unstable microscopic bubbles to dissolve. | 12-09-2010 |
20110199842 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 08-18-2011 |
20110221002 | MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF - The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow. | 09-15-2011 |
20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
20110248354 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects. | 10-13-2011 |
20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
20110254058 | Gate-All-Around CMOSFET devices - A GAA (Gate-All-Around) CMOSFET device includes a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The surfaces of the first channel and the second channel are substantially surrounded by the gate region. A buried insulation layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the semiconductor substrate to isolate them from one another. The structure is simple, compact and highly integrated, has high carrier mobility, and avoids polysilicon gate depletion and short channel effect. | 10-20-2011 |
20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 10-20-2011 |
20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 10-20-2011 |
20110259752 | METHOD FOR SUBSTANTIALLY UNIFORM COPPER DEPOSITION ONTO SEMICONDUCTOR WAFER - The methods practiced in an electrochemical deposition apparatus with two or more electrodes, described in earlier inventions, are disclosed. The methods produce uniform copper films with WFNU less than 2.5% on semiconductor wafers bearing a resistive copper seed layer with a thickness ranging from 50 to 9O0 A in a copper sulfate based electrolyte whose conductivity is between 0.02 to 0.8 S/cm. | 10-27-2011 |
20110291191 | MOS Structure with Suppressed SOI Floating Body Effect and Manufacturing Method thereof - The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process. | 12-01-2011 |
20110292723 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 12-01-2011 |
20120009741 | SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology. | 01-12-2012 |
20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 01-19-2012 |
20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 01-26-2012 |
20120021571 | Method of Reducing Floating Body Effect of SOI MOS Device Via a Large Tilt Ion Implantation - The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process. | 01-26-2012 |
20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 02-02-2012 |
20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
20120115287 | MANUFACTURING METHOD OF SOI MOS DEVICE ELIMINATING FLOATING BODY EFFECTS - The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below. The present invention utilizes the silicide and the heavily doped P-type region to form an ohmic contact in order to release the holes accumulated in the body region of SOI MOS device and eliminate SOI MOS floating body effects. Besides, the manufacturing process is simple and can be easily implement. Further, the manufacturing process according to the present invention will not increase chip area and is compatible with conventional CMOS process. | 05-10-2012 |
20120129320 | METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER - The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance. | 05-24-2012 |
20120205743 | PD SOI DEVICE WITH A BODY CONTACT STRUCTURE - The present invention discloses a PD SOI device with a body contact structure. The active region of the PD SOI device includes: a body region; a gate region, which is inverted-L shaped, formed on the body region; a N-type source region and a N-type drain region, formed respectively at the two opposite sides of the anterior part the body region; a body contact region, formed at one side of the posterior part of the body region, which is side-by-side with the N-type source region; and a first silicide layer, formed on the body contact region and the N-type source region, which is contact to both of the body contact region and the N-type source region. The body contact region of the device is formed on the border of the source region and the leading-out terminal of the gate electrode. It can suppress floating body effect of the PD SOI device meanwhile not increasing the chip area, thereby overcoming the shortcoming in the prior art that the chip area is enlarged when the traditional body contact structure is employed. Furthermore, the fabrication process provided herein is simple and compatible to the CMOS technology. | 08-16-2012 |
20130029478 | METHOD OF FABRICATING HIGH-MOBILITY DUAL CHANNEL MATERIAL BASED ON SOI SUBSTRATE - The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation. | 01-31-2013 |
20130054209 | Modeling Method of SPICE Model Series of SOI FET - The present invention provides a modeling method of a SPICE model series of a Silicon On Insulator (SOI) Field Effect Transistor (FET), where auxiliary devices are designed and fabricated, electrical property data is measured, intermediate data is obtained, model parameters are extracted based on the intermediate data, a SPICE model of an SOI FET of a floating structure is established, model parameters are extracted by using the intermediate data and data of the auxiliary devices, a macro model is complied, and a SPICE model of an SOI FET of a body leading-out structure is established. The modeling method provided in the present invention takes an influence of a parasitic transistor of a leading-out part in a body leading-out structure into consideration, and model series established by using the method can more accurately reflect actual operating conditions and electrical properties of the SOI FET of a body leading-out structure and the SOI FET of a floating structure, thereby improving fitting effects of the models. | 02-28-2013 |
20130054210 | Method for Determining BSIMSOI4 DC Model Parameters - The present invention provides a method for determining BSIMSOI4 Direct Current (DC) model parameters, where a plurality of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices of a body leading-out structure and of different sizes, and a plurality of MOSFET devices of a floating structure and of different sizes are provided; Id-Vg-Vp, Id/Ip-Vd-Vg, Ig-Vg-Vd, Ig-Vp, Ip-Vg-vd, Is/Id-Vp, and Id/Ip-Vp-Vd properties of all the MOSFET devices of a body leading-out structure, and Id-Vg-Vp, Id-Vd-Vg, and Ig-Vg-Vd properties of all the MOSFET devices of a floating structure are measured; electrical property curves without a self-heating effect of each MOSFET device of a body leading-out structure and each MOSFET device of a floating structure are obtained; and then DC parameters of a BSIMSOI4 model are successively extracted according to specific steps. In the present invention, proper test curves are successively selected according to model equations, and various kinds of parameters are successively determined, thereby accurately and effectively extracting the DC parameters of the BSIMSOI4 model. | 02-28-2013 |
20130054219 | Equivalent Electrical Model of SOI FET of Body Leading-Out Structure, and Modeling Method Thereof - The present invention provides an equivalent electrical model of a Silicon On Insulator (SOI) Field Effect Transistor (FET) of a body leading-out structure, and a modeling method thereof. The equivalent electrical model is formed by an internal FET and an external FET connected in parallel, where the SOI FET of a body leading-out structure is divided into a body leading-out part and a main body part, the internal FET represents a parasitic transistor of the body leading-out part, and the external FET represents a normal transistor of the main body part. The equivalent electrical model provided in the present invention completely includes the influence of parts of a physical structure of the SOIMOSFET device of a body leading-out structure, that is, the body leading-out part and the main body part, on the electrical properties, thereby improving a fitting effect of the model on the electrical properties of the device. | 02-28-2013 |
20130062696 | SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof - The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure. | 03-14-2013 |
20130152033 | TCAD Emulation Calibration Method of SOI Field Effect Transistor - The present invention provides a Technology Computer Aided Design (TCAD) emulation calibration method of a Silicon On Insulator (SOI) field effect transistor, where process emulation Metal Oxide Semiconductor (MOS) device structures with different channel lengths Lgate are obtained by establishing a TCAD process emulation program; based on the process emulation MOS device structures, the process emulation MOS device structures are calibrated according to a Transmission Electron Microscope (TEM) test result, a secondary ion mass spectrometer (SIMS) test result, a Capacitor Voltage (CV) test result, a WAT test result, and a square resistance test result of an actual device, so as to complete TCAD emulation calibration of key electrical parameters of an SOI field effect transistor. Through the calibration method consistent with the present invention, in the same SOI process, TCAD emulation results of key parameters Vt and Idsat of MOSFETs of different sizes all meet a high-precision requirement that an error is less than 10%; moreover, accurate and effective pretest can be implement in the case of multiple splits, thereby providing effective guidance for research, development and optimization of a new process flow. | 06-13-2013 |
20130167605 | AQUEOUS SOLUTION LUBRICANT FOR ALUMINUM COLD ROLLING - Compositions related to a water-based lubricant fluid for aluminum cold rolling which is free from measurable particles or oil droplets which can be applied in field production. A single-phase lubricant fluid may include water-soluble polymers, lubricating additives, anti-rust additives, anti-oxidant additives, pH-adjust additives, or combinations thereof. | 07-04-2013 |
20130264609 | Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof - The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor. The preparation method includes: preparing a Ge semiconductor layer on a bulk silicon substrate; preparing a group III-V semiconductor material layer on the Ge semiconductor layer; performing first photolithography and etching to make a patterned window to a Ge layer so as to form a recess; preparing a spacer in the recess; preparing a Ge film through selective epitaxial growth; performing chemical mechanical polishing to obtain a heterogeneously integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar; removing the spacer and a defect part of the Ge layer close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high performance CMOS device including a Ge channel PMOS and a group III-V channel NMOS by forming an MOS structure. | 10-10-2013 |
20130273714 | METHOD FOR PREPARING SEMICONDUCTOR SUBSTRATE WITH INSULATING BURIED LAYER BY GETTERING PROCESS - A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded. | 10-17-2013 |
20140216940 | METHODS AND APPARATUS FOR UNIFORMLY METALLIZATION ON SUBSTRATES - An apparatus for substrate metallization from electrolyte is provided. The apparatus comprises: an immersion cell containing metal salt electrolyte; at least one electrode connecting to at least one power supply; an electrically conductive substrate holder holding at least one substrate to expose a conductive side of the substrate to face the at least one electrode; an oscillating actuator for oscillating the substrate holder with an amplitude and a frequency; at least one ultrasonic device with an operating frequency and an intensity, disposed in the metallization apparatus; at least one ultrasonic power generator connecting to the ultrasonic device; at least one inlet for metal slat electrolyte feeding; and at least one outlet for metal salt electrolyte draining. | 08-07-2014 |