Patent application number | Description | Published |
20080235679 | Loading Software on a Plurality of Processors - Loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution. | 09-25-2008 |
20090216998 | Apparatus for and Method of Processor to Processor Communication for Coprocessor Functionality Activation - A novel and useful mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication. | 08-27-2009 |
20100049883 | METHOD AND SYSTEM FOR MEMORY ADDRESS TRANSLATION AND PINNING - A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame as long as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway. | 02-25-2010 |
20100058358 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic executes the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 03-04-2010 |
20110208949 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 08-25-2011 |
20120185678 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 07-19-2012 |
20130007408 | METHOD AND APPARATUS FOR MANAGING SOFTWARE CONTROLLED CACHE OF TRANSLATING THE PHYSICAL MEMORY ACCESS OF A VIRTUAL MACHINE BETWEEN DIFFERENT LEVELS OF TRANSLATION ENTITIES - A method and a system for allowing a guest operating system (guest OS) to modify an entry in a TLB directly without an involvement of a hypervisor are disclosed. Upon receiving a guest TLB miss exception, a guest OS issues a TLBWE (TLB Write Entry) instruction to logic. The logic runs the TLBWE instruction at a supervisor mode without invoking a hypervisor. The TLB may incorporate entries in a guest page table and entries in a host page table. | 01-03-2013 |
Patent application number | Description | Published |
20140040577 | Automatic Use of Large Pages - A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully. | 02-06-2014 |
20140074960 | COMPACTING A NON-BIASED RESULTS MULTISET - A method, system, and computer program product for compacting a non-biased results multiset are provided in the illustrative embodiments. A set of references and a multiset of values are identified. The multiset includes a first and a second set of values, each set including a first value. A first reference in the set of references refers to the first set of values and a second reference in the set of references refers to the second set of values. The values in the first and second set of values are re-arranged to form permuted first and second sets of values. The multiset is compacted by overlaying the permuted first and second sets of values in a portion such that the permuted first set of values and the permuted second set of values share a single instance of the first value in a portion of the compacted multiset. | 03-13-2014 |
20150127767 | RESOLVING CACHE LOOKUP OF LARGE PAGES WITH VARIABLE GRANULARITY - A method, system, and computer program product for resolving cache lookup of large pages with variable granularity are provided in the illustrative embodiments. A number of unused bits in an available number of bits is identified. The available number of bits is configured to address a page of data in memory, wherein the page exceeding a threshold size, and the page comprising a set of parts. The unused bits are mapped to the plurality of parts such that a value of the unused bits corresponds to existence of a subset of the set of parts in a memory. A virtual address is translated to a physical address of a requested part in the set of parts. A determination is made, using the unused bits, whether the requested part exists in the memory. | 05-07-2015 |