Wu, Zhubei City
Andy Wu, Zhubei City TW
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20120104450 | LIGHT EMITTING DIODE OPTICAL EMITTER WITH TRANSPARENT ELECTRICAL CONNECTORS - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 05-03-2012 |
20140093990 | Light Emitting Diode Optical Emitter with Transparent Electrical Connectors - An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching. | 04-03-2014 |
Bo-Chang Wu, Zhubei City TW
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20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
Chang-Cherng Wu, Zhubei City TW
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20150346447 | OPTICAL CABLE MODULE - An optical cable module is disclosed. The optical cable module comprises a connector and an optical cable, and the optical cable is connected to the connector. The optical cable comprises at least one optical fiber, an outer cladding layer and a power line, and the outer cladding layer surrounds the at least one optical fiber and the power line, and the power line is configured to supply an electrical power. | 12-03-2015 |
20150346448 | OPTICAL CABLE MODULE AND METHOD FOR MANUFACTURING THE SAME - An optical cable module and a method for manufacturing the same are disclosed. The optical cable module comprises a connector and an optical cable, and the optical cable is connected to the connector. A wavelength of at least one optical signal emitted from a laser of the connector is in a range of 380 nm to 980 nm. The optical cable comprises at least one optical fiber and an outer cladding layer, and the outer cladding layer surrounds the optical fiber, and the outer cladding layer includes at least one transparent portion, and at least one portion of the optical signal is leaked from the optical fiber and passes through the transparent portion to the surrounding environment. | 12-03-2015 |
Chang-Yu Wu, Zhubei City TW
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20150340944 | LIGHT EMITTING DEVICE DRIVER CIRCUIT, CURRENT RIPPLE REJECTER THEREIN, AND CURRENT RIPPLE REJECTION METHOD THEREFOR - The present invention discloses a light emitting device driver circuit, a current ripple rejecter therein, and a current ripple rejection method therefor. The light emitting device driver circuit includes: a power converter circuit, for converting an input voltage carrying an AC component to an output voltage and supplying an output current; and a current ripple rejecter, which is coupled to the power converter circuit, for filtering a ripple of the output current to generate a light emitting device current, and supplying the light emitting device current to a light emitting device circuit. The current ripple rejecter includes: a low-pass-filter circuit, for filtering the ripple of the output current to generate a filtered current; and a current amplification circuit, which is coupled to the low-pass-filter circuit, for amplifying the filtered current to generate an amplified current; wherein the light emitting device current includes the amplified current. | 11-26-2015 |
20160021715 | LIGHT EMITTING DEVICE DRIVER CIRCUIT AND CONTROL CIRCUIT AND CONTROL METHOD THEREOF - The present invention provides a light emitting device driver circuit and a control circuit and a control method thereof. The light emitting device driver circuit is used for driving a light emitting device circuit according to a rectified dimming signal. The light emitting device driver circuit includes a power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) circuit, a current limit (CL) circuit, and a determination circuit. The CL circuit generates a CL signal according to a current sense signal and a predetermined CL threshold. The determination circuit is coupled to the PWM circuit and the CL circuit, for generating an operation signal according to a PWM signal and the CL signal. The power stage circuit maintains an absolute level of an AC dimming current not lower than a holding current in an ON phase period. | 01-21-2016 |
20160141966 | FLYBACK POWER CONVERTER, SECONDARY SIDE CONTROL CIRCUIT, AND CONTROL METHOD THEREOF - The present invention provides a flyback power converter, a secondary side control circuit, and a control method thereof. The flyback power converter converts an input voltage to an output voltage, and provides a load current to a load circuit. The flyback power converter includes: a transformer circuit, a power switch circuit, a switch current sense circuit, a primary side control circuit, and a secondary side control circuit. The secondary side control circuit adaptively adjusts a frequency of a zero of a compensator gain function and/or a mid-frequency gain of the compensator gain function according to the load current, such that a number of poles of a system open loop gain function of the flyback power converter is at most more than a number of zeroes of the system open loop gain function by one under a crossover frequency. | 05-19-2016 |
Chen-Bau Wu, Zhubei City TW
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20080211026 | Coupling well structure for improving HVMOS performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 09-04-2008 |
20090142898 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 06-04-2009 |
20100203691 | High Voltage CMOS Devices - A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation. | 08-12-2010 |
20110006366 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 01-13-2011 |
20120037987 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 02-16-2012 |
20140045304 | Coupling Well Structure for Improving HVMOS Performance - A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric. | 02-13-2014 |
Cheng-Ju Wu, Zhubei City TW
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20130064263 | VERTICAL CAVITY SURFACE EMITTING LASER AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of vertical cavity surface emitting laser. The method includes following steps: providing a substrate; forming an epitaxial layer stack including an aluminum-rich layer; forming an ion-doping mask including a ring-shaped opening; doping ions in the epitaxial layer stack through the ring-shaped opening and forming a ring-shaped ion-doped region over the aluminum-rich layer; forming an etching mask on the ion-doping mask for covering the ring-shaped opening of the ion-doping mask; etching the epitaxial layer stack through the etching mask and ion-doping mask for forming an island platform; oxidizing the aluminum-rich layer for forming a ring-shaped oxidized region. In addition, the present invention also discloses a vertical cavity surface emitting laser manufactured by the above mentioned method. | 03-14-2013 |
Chia-Yu Wu, Zhubei City TW
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20150293141 | MIRCO-ELECTRO-MECHANICAL SYSTEM DEVICE - The present invention discloses a micro-electro-mechanical system (MEMS) device. The MEMS device includes: a substrate; a proof mass which defines an internal space inside and forms at least two capacitors with the substrate; at least two anchors connected to the substrate and respectively located in the capacitor areas of the capacitors from a cross-sectional view; at least one linkage truss located in the hollow structure, wherein the linkage truss is directly connected to the anchors or indirectly connected to the anchors through buffer springs; and multiple rotation springs located in the hollow structure, wherein the rotation springs are connected between the proof mass and the linkage truss, such that the proof mass can rotate along an axis formed by the rotation springs. There is no coupling mass which does not form a movable electrode in the connection between the proof mass and the substrate. | 10-15-2015 |
Ching-Huei Wu, Zhubei City TW
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20160108991 | COMBINED TRANSMISSION SHAFT AND ROTATING DEVICE HAVING COMBINED TRANSMISSION SHAFT - A rotating device includes a rotating disc and a combined transmission shaft. The rotating disc includes a turret and multiple driven rollers. The combined transmission shaft includes a first roller gear cam and a second roller gear cam. The first roller gear cam includes a first shaft, a combined shaft and a first helical tooth. The combined shaft protrudes outward from a side of the first shaft. The first shaft is surrounded by the first helical tooth and has a first outer surface and a first inner surface. The second roller gear cam includes a second shaft and a second helical tooth. The second shaft has a combination hole. The second shaft is surrounded by the second helical tooth and has a second outer surface and a second inner surface. The combined shaft passes through the combination hole. | 04-21-2016 |
Ching-I Wu, Zhubei City TW
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20110144326 | Method for manufacturing stereoselective preparation of 4-BMA using a chiral auxiliary and chiral auxiliary - The present invention relates to a process for preparing (3R,4S)-3-[[[R]-1′-t-butyldimethylsilyloxy]ethyl]-4-[(R)-1″-carboxyethyl]-2-azetidinone (beta-methylazetidin-2-one; 4-BMA), a key intermediate for the synthesis of carbapenem and penem antibiotics. Specifically, the present invention relates to a process comprising first, the preparation of a chiral auxiliary from cheap L-Phenylalaninol, and then the preparation of 4-BMA in high yield and high selectivity, under industrially mild condition. | 06-16-2011 |
Chin-Nan Wu, Zhubei City TW
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20140111435 | CURSOR CONTROL DEVICE AND METHOD USING THE SAME TO LAUNCH A SWIPE MENU OF AN OPERATING SYSTEM - A cursor control device has a touch control module for users to perform a swipe gesture. The touch control module generates a control command according to the swipe gesture and transmits the control command to a host computer. The host computer then launches a swipe menu on an edge of a display screen thereof Accordingly, after a host computer with the Win8™ installed therein as the operating system receives the control command, the edge swipe function supported by the Win8™ can be launched. | 04-24-2014 |
Chung-Wen Wu, Zhubei City TW
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20140203445 | MITIGATING PATTERN COLLAPSE - One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example. | 07-24-2014 |
20140252625 | Method of Preventing a Pattern Collapse - A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1 | 09-11-2014 |
20140264873 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 09-18-2014 |
20140264902 | Novel Patterning Approach for Improved Via Landing Profile - The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues. | 09-18-2014 |
20140264926 | Method and Apparatus for Back End of Line Semiconductor Device Processing - A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature. | 09-18-2014 |
20140264932 | Patterning Approach to Reduce Via to Via Minimum Spacing - A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches. | 09-18-2014 |
20150262934 | Patterning Approach to Reduce Via to Via Minimum Spacing - A method for patterning vias in a chip comprises forming a photomask layer including a gap on a patterned hardmask layer including a plurality of trenches and in contact with a uniform layer on a substrate, wherein the gap overlaps with two or more of the trenches. The method further comprises exposing a portion of the uniform layer under the gap using a photo exposure process, etching the exposed portion of the uniform layer with the photomask layer to obtain a plurality of vias extended partially through the substrate, and further etching the vias to obtain corresponding through-substrate vias. Another method comprises patterning a plurality of vias in a plurality of trenches of a hardmask layer on a substrate using a single photo exposure step and a photomask comprising a single gap that overlaps with the trenches. | 09-17-2015 |
20150311152 | Interconnection Structure And Method For Semiconductor Device - A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer. | 10-29-2015 |
20160027688 | Method Of Preventing Pattern Collapse - A device includes a substrate and at least three conducting features embedded into the substrate. Each conducting feature includes a top width x and a bottom width y, such that a top and bottom width (x1, y1) of a first conducting feature has a dimension of (x1 | 01-28-2016 |
Jen-Ming Wu, Zhubei City TW
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20100315176 | ACTIVE BACK-END TERMINATION CIRCUIT - The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with V | 12-16-2010 |
Jui-Jen Wu, Zhubei City TW
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20130107609 | Static Random Access Memory Cell | 05-02-2013 |
20140043886 | SENSING MEMORY ELEMENT LOGIC STATES FROM BIT LINE DISCHARGE RATE THAT VARIES WITH RESISTANCE - A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch. | 02-13-2014 |
20140184300 | Multiple Power Domain Circuit and Related Method - A multiple power domain circuit includes a trigger circuit, a high threshold voltage circuit electrically connected to an output terminal of the trigger circuit, and a low threshold voltage circuit electrically connected to the output terminal of the trigger circuit and an output terminal of the high threshold voltage circuit. The low threshold voltage circuit comprises a pulse generator electrically connected to the output terminal of the trigger circuit, and an inverter electrically connected to an output terminal of the pulse generator, and the output terminal of the high threshold voltage circuit. | 07-03-2014 |
20140241101 | Word Line Driver and Related Method - A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor. | 08-28-2014 |
20150016198 | Multiple Power Domain Circuit and Related Method - A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit. | 01-15-2015 |
Kuang-Cheng Wu, Zhubei City TW
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20140042553 | PROFILE PRE-SHAPING FOR REPLACEMENT POLY GATE INTERLAYER DIELECTRIC - Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed. | 02-13-2014 |
20140349471 | PROFILE PRE-SHAPING FOR REPLACEMENT POLY GATE INTERLAYER DIELECTRIC - Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate having an upper surface with a source region and drain region proximate thereto. A channel region is disposed in the substrate between the source region and the drain region. A gate electrode is disposed over the channel region and separated from the channel region by a gate dielectric. Sidewall spacers are formed about opposing sidewalls of the gate electrode. Upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers. A liner is disposed about opposing sidewalls of the sidewall spacers and has a first thickness at an upper portion of liner and a second thickness at a lower portion of the liner. The first thickness is less than the second thickness. Other embodiments are also disclosed. | 11-27-2014 |
Kun-Hua Wu, Zhubei City TW
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20140268877 | LUMINOUS ELEMENT, BAR-TYPE LUMINOUS ELEMENT AND APPLICATIONS THEREOF - A luminous element includes a heat dissipation plate, a body, a plurality of LED chips, a first connector and a second connector. The heat dissipation plate includes a die-bonding area and a heat dissipation area opposite to the die-bonding area. The body surrounds the heat dissipation plate, and includes a first body surface and a second body surface opposite to the first body surface. The first body surface includes a concave part exposing the die-bonding area. The second body surface includes an opening exposing the heat dissipation area. The LED chips are mounted on the die-bonding area. The first and the second connectors are disposed on the body, and they can be pluggably connected to an external power source or other connectors. The LED chips are connected to the electrical input terminals in the first and the second connectors. | 09-18-2014 |
20150062922 | LENS DEVICE AND LIGHT SOURCE MODULE USING THE SAME - A lens device and a light source module using the same are provided. The lens device comprises a lens and a patterned light shielding layer. The lens has a middle light emitting surface and a periphery light emitting surface surrounding the middle light emitting surface. The patterned light shielding layer is formed on the periphery light emitting surface of the lens. | 03-05-2015 |
20150124476 | LIGHTING APPARATUS AND WAVELENGTH CONVERTING APPARATUS THEREOF - A lighting apparatus includes a wavelength converting apparatus. The wavelength converting apparatus includes a hollow tube and a wavelength converting material. The hollow tube has an accommodating chamber. The wavelength converting material is positioned in the accommodating chamber. | 05-07-2015 |
Kun-Tai Wu, Zhubei City TW
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20120003817 | INTEGRATED CIRCUIT WAFER DICING METHOD - An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies. | 01-05-2012 |
20120018880 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer, a bump, and a metal layer. The metal wiring layer is formed on the die body while the bump is formed on the metal wiring layer during the semiconductor front-end-of-line (FEOL) process and protrudes from the die body. The metal layer is disposed on one side of the bump opposite to the metal wiring layer, wherein the activity of the metal layer is smaller than the activity of the bump. In this way, the semiconductor structure of the present invention is easy to be manufactured and the manufacture cost is also reduced. | 01-26-2012 |
20120168752 | TESTKEY STRUCTURE, CHIP PACKAGING STRUCTURE, AND METHOD FOR FABRICATING THE SAME - The invention provides a testkey structure for testing a chip. The testkey structure includes a metal pad and a first groove, wherein the first groove is disposed on the metal pad. The first groove is located between a first signal lead and a second signal lead of the chip. According to the first groove, the first signal lead and the second signal lead could be separated from each other to prevent the first signal lead and the second signal lead from shorting. | 07-05-2012 |
Kuo-Yu Wu, Zhubei City TW
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20130320418 | Self-Aligned Implantation Process for Forming Junction Isolation Regions - A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation. | 12-05-2013 |
Pochi Wu, Zhubei City TW
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20110207315 | METHOD OF FABRICATING GATE STRUCTURES - An embodiment of the disclosure includes a method of forming metal gate structures. A substrate is provided. A first dummy gate electrode and a second dummy gate electrode are formed on the substrate. The first dummy gate electrode comprises first spacers on its sidewalls and the second dummy gate electrode comprises second spacers on its sidewalls. A hardmask layer is formed to covers both the first dummy gate electrode and the second dummy gate electrode. A patterned photoresist layer on the hardmask layer that covers a portion of the hardmask layer over the second dummy gate electrode and that leaves a portion of the hardmask layer over the first dummy gate electrode exposed. The portion of the exposed hardmask layer over the first dummy gate electrode is removed. The first spacers and the first dummy gate electrode is exposed to a first plasma environment comprising O2, HBr, and Cl | 08-25-2011 |
Po-Chi Wu, Zhubei City TW
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20130105915 | METAL OXIDE SEMICONDUCTOR DEVICE HAVING A PREDETERMINED THRESHOLD VOLTAGE AND A METHOD OF MAKING | 05-02-2013 |
20130146993 | SEMICONDUCTOR STRUCTURE HAVING A POLYSILICON STRUCTURE AND METHOD OF FORMING SAME - The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure. | 06-13-2013 |
20130181262 | Performing Treatment on Stressors - A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region. | 07-18-2013 |
20150187939 | Metal Gate Transistor and Method for Tuning Metal Gate Profile - A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile. | 07-02-2015 |
20160043079 | Semiconductor Device and Method of Manufacture - In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged. | 02-11-2016 |
20160104704 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance. | 04-14-2016 |
20160111543 | Metal Gate with Silicon Sidewall Spacers - A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening. | 04-21-2016 |
Po-Hao Wu, Zhubei City TW
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20160037095 | ACTIVE PIXEL SENSOR DEVICE AND OPERATING METHOD OF THE SAME - An active pixel sensor device and the method thereof include an active pixel sensing array and a synchronous reading circuit. The active pixel sensing array is formed by a plurality of sensing pixels disposed in a form of an array. Each sensing pixel has a power terminal. The synchronous reading circuit connects to the power terminals of all sensing pixels, detects a summation of currents flowing through all sensing pixels, converts the summation of currents to an output signal, and outputs the output signal that represents the optical sensing information. In addition to reading each sensing pixel, the active pixel sensor device further controls the synchronous reading circuit to read the output signal corresponding to the summation of currents of all sensing pixels. The active pixel sensor device using the same active pixel sensing array can be applied to large-area sensing. | 02-04-2016 |
20160050378 | PIXEL SENSOR DEVICE AND OPERATING METHOD THEREOF - A pixel sensor device has a first sensing unit, a second sensing unit, a first control and reading unit, and a second control and reading unit. The first and second sensing units are disposed concentrically. The first and second control and reading units are connected respectively to the first and second sensing units for separately or simultaneously controlling the first and second sensing units to perform sensing. Since the first and second sensing units are formed by a single pixel sensing array and arranged concentrically, only a single focusing element is required to align centers of the first and second sensing units during the manufacturing process. This achieves high focus accuracy and increases precision in recognition. In the applications of fingerprint recognition and pulse measurement, the user only uses a single finger for sensing so that inaccurate focusing resulted from moving finger is avoided. | 02-18-2016 |
Shan Hua Wu, Zhubei City TW
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20110020975 | METHOD FOR MANUFACTURING PHOTODIODE DEVICE - A method of manufacturing photodiode device includes the following steps: providing a wafer having a substrate and an epitaxy layer, the substrate having a first surface and a second surface and the epitaxy layer formed on the first surface; forming a first conductive layer on the second surface of the substrate; forming a patterned conductive layer above the epitaxy layer; and etching the patterned conductive layer by a reactive ion etching (RIE) process performed under argon gas and helium gas. | 01-27-2011 |
20110284983 | PHOTODIODE DEVICE AND MANUFACTURING METHOD THEREOF - A photodiode device and the manufacturing method of the same are provided. The photodiode device includes a substrate; an epitaxy layer on the substrate, the epitaxy layer including a window layer and a cap layer on the window layer, the cap layer covering a portion of the window layer; and a patterned conductive layer on the cap layer, the patterned conductive layer being formed with a bottom area and a top area wherein the bottom area is greater than the top area. | 11-24-2011 |
Sheng-Wei Wu, Zhubei City TW
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20150053136 | Vertical Furnace for Improving Wafer Uniformity - A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube. | 02-26-2015 |
Shih-Chi Wu, Zhubei City TW
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20120020436 | Method and device for multi-channel data alignment in transmission system - A method and a device for multi-channel data alignment in a transmission system are provided, wherein the method comprises receiving a first stream data and a second stream data, determining a deleting/inserting state of the first stream data and the second stream data to generate an information of mismatch data due to a speed difference situation, generating a reverse inserting control signal or a reverse deleting control signal to completely restore the original first stream data and/or the original second stream data at a transmission end, deleting/inserting the first stream data and the second stream data simultaneously after receiving the deleting/inserting state of the first stream data and the second stream data, and outputting the corrected first stream data and the corrected second stream data without mismatching. | 01-26-2012 |
20130111083 | PCS ARCHITECTURE | 05-02-2013 |
Sin-Hua Wu, Zhubei City TW
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20110237040 | MAIN SPACER TRIM-BACK METHOD FOR REPLACEMENT GATE PROCESS - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 09-29-2011 |
20120009754 | METHOD FOR MAIN SPACER TRIM-BACK - The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges. | 01-12-2012 |
20130154022 | CMOS Devices with Metal Gates and Methods for Forming the Same - A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device. | 06-20-2013 |
20130323893 | Methods for Forming MOS Devices with Raised Source/Drain Regions - A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor. | 12-05-2013 |
20140048886 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity. | 02-20-2014 |
Tai-Ting Wu, Zhubei City TW
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20110099133 | Systems and methods for capturing and managing collective social intelligence information - A method for capturing and managing training data collected online includes: receiving a first dataset from one or more online sources; sampling the first dataset and generating a second dataset, the second dataset including the data sampled from the first dataset; receiving an annotated second dataset with predefined labels; and dividing the annotated second dataset into a training dataset and a test dataset. The disclosed method further includes: configuring a machine learning based classifier based on the training dataset; predicting at least one data point based on the training dataset and calculating a confidence score; comparing the at least one predicted data point to the test dataset; sorting the at least one predicted data point based on its confidence score; and receiving corrected training data associated with the at least one predicted data point. | 04-28-2011 |
20110112995 | Systems and methods for organizing collective social intelligence information using an organic object data model - A method for capturing and organizing intelligence data using an organic data model includes: receiving one or more webpages containing social intelligence data; segmenting content of the one or more webpages containing social intelligence data; identifying named entities in the segmented content of the one or more webpages; identifying topics in the segmented content of the one or more webpages; identifying opinions in the segmented content of the one or more webpages; integrating the identified named entities, topics, and opinions to construct an organic object data model; and storing organic object data associated with the constructed organic object data model in an organic object database. | 05-12-2011 |
20130156324 | GEOGRAPHICAL LOCATION RENDERING SYSTEM AND METHOD AND COMPUTER READABLE RECORDING MEDIUM - A geographical location rendering method executed in a geographical location rendering system for identifying at least one semantic region is provided. A density clustering is performed on a plurality of user generated contents of respective geographical location name information to generate a plurality of region candidates. A name extraction is performed on the region candidates to extract and confirm a common region name of the region candidates as a name of the semantic region. A region scope of the region candidates is detected as a location scope of the semantic region according to a spatial density analysis. | 06-20-2013 |
Tao-Cheng Wu, Zhubei City TW
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20100086148 | APPARATUS AND METHOD FOR PROCESSING AUDIO SIGNAL - An apparatus for processing an audio input signal is provided and includes an audio processing circuit and an audio compressing circuit. The audio processing circuit receives the audio input signal, and enhances a first frequency part of the audio input signal to output a bass-enhancement signal. The audio compressing circuit is coupled to the audio processing circuit, and reduces a gain of a second frequency part of the bass-enhancement signal to output an audio output signal. | 04-08-2010 |
Tsung-Nan Wu, Zhubei City TW
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20130336420 | Method of Transmission through Single Wire - The invention provides a method of transmission through single wire. The method includes receiving a single-wire signal through a single wire; identifying a start code of the single-wire signal; after identifying the start code, counting a rising edge, a falling edge, or both rising edge and falling edge of the single-wire signal in at least one bit transmission period having a fixed length, to generate a count code; and decoding the count code to generate transmitted information. | 12-19-2013 |
20150145585 | Sample Rate Converter and Rate Estimator Thereof and Rate Estimation Method Thereof - A sample rate converter receives an input signal with an input sample rate, and generates an output signal with an output sample rate. The sample rate converter includes: a rate estimator, a polynomial interpolation calculation circuit, an up sampling filter, and a down sampling filter. The rate estimator includes: a subtractor, which generates an error signal according to an input clock signal and a second order rate signal; a first order integrator, which generates a first order rate signal according to the error signal; and a second order integrator, which generates the second order rate signal according to the first order rate signal. | 05-28-2015 |
Wei Cheng Wu, Zhubei City TW
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20120001259 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess. | 01-05-2012 |
20130069174 | CONTACT FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material. | 03-21-2013 |
20130154022 | CMOS Devices with Metal Gates and Methods for Forming the Same - A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device. | 06-20-2013 |
20130264652 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 10-10-2013 |
20130285151 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 10-31-2013 |
20130299913 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 11-14-2013 |
20130328115 | Contact for High-K Metal Gate Device - An integrated circuit includes a semiconductor substrate including a source region and a drain region and a gate dielectric over the semiconductor substrate. A metal gate structure is over the semiconductor substrate and the gate dielectric and between the source and drain regions. The integrated circuit further includes an interlayer dielectric (ILD) over the semiconductor substrate. First and second contacts extend through the ILD and adjacent the source and drain regions, respectively, and a third contact extends through the ILD and adjacent a top surface of the metal gate structure. The third contact further extends into an undercut region of the metal gate structure. | 12-12-2013 |
20140103429 | Method and Structure to Boost MOSFET Performance and NBTI - The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pFET) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well (n-well) in the semiconductor region by performing an ion implantation of a n-type dopant to the semiconductor substrate through the opening of the mask layer; and performing a germanium (Ge) channel implantation to the semiconductor substrate through the opening of the mask layer, forming a Ge channel implantation region in the n-well. | 04-17-2014 |
20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 09-04-2014 |
20140252455 | Structure And Method For Static Random Access Memory Device Of Vertical Tunneling Field Effect Transistor - The present disclosure provides one embodiment of a SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters. The pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 09-11-2014 |
20140252504 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well. | 09-11-2014 |
20140264725 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots. | 09-18-2014 |
20140353794 | SEMICONDUCTOR ARRANGEMENT AND METHOD OF FORMING - A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided. | 12-04-2014 |
20140374814 | Embedded Memory and Methods of Forming the Same - An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer. | 12-25-2014 |
20140374815 | Memory Devices with Floating Gate Embedded in Substrate - An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack. | 12-25-2014 |
20150021672 | CONTACT FOR HIGH-K METAL GATE DEVICE - An integrated circuit having an improved gate contact and a method of making the circuit are provided. In an exemplary embodiment, the method includes receiving a substrate. The substrate includes a gate stack disposed on the substrate and an interlayer dielectric disposed on the gate stack. The interlayer dielectric is first etched to expose a portion of the gate electrode, and then the exposed portion of the gate electrode is etched to form a cavity. The cavity is shaped such that a portion of the gate electrode overhangs the electrode. A conductive material is deposited within the cavity and in electrical contact with the gate electrode. In some such embodiments, the etching of the gate electrode forms a curvilinear surface of the gate electrode that defines the cavity. | 01-22-2015 |
20150048433 | Contact Formation for Split Gate Flash Memory - An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array. | 02-19-2015 |
20150091072 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 04-02-2015 |
20150129952 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal. | 05-14-2015 |
20150129969 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first area and a second area divided by a shallow trench isolation (STI) area, a first dummy structure on the STI area, a second dummy structure located on the STI area, a first semiconductor structure on the first area, and a second semiconductor structure on the second area of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a high-k dielectric first, high-k metal gate last procedure. | 05-14-2015 |
20150137206 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 05-21-2015 |
20150137207 | Flash Memory Embedded with HKMG Technology - An integrated circuit structure includes a flash memory cell and a logic MOS device. The flash memory cell includes a floating gate dielectric, a floating gate overlying the floating gate dielectric, a control gate overlying the floating gate, a word-line on a first side of the floating gate and the control gate, and an erase gate on a second side of the floating gate and the control gate. The logic MOS device includes a high-k gate dielectric, and a gate electrode over the high-k gate dielectric. The gate electrode, the control gate, the word-line, and the erase gate are formed of a same metal-containing material, and have top surfaces coplanar with each other. | 05-21-2015 |
20150145022 | CMP FABRICATION SOLUTION FOR SPLIT GATE MEMORY EMBEDDED IN HK-MG PROCESS - A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate. | 05-28-2015 |
20150155286 | Structure and Method For Statice Random Access Memory Device of Vertical Tunneling Field Effect Transistor - Forming an SRAM cell that includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least one pull-down devices; and at least two pass-gate devices configured with the two cross-coupled inverters, the pull-up devices, the pull-down devices and the pass-gate devices include a tunnel field effect transistor (TFET) that further includes a semiconductor mesa formed on a semiconductor substrate and having a bottom portion, a middle portion and a top portion; a drain of a first conductivity type formed in the bottom portion and extended into the semiconductor substrate; a source of a second conductivity type formed in the top portion, the second conductivity type being opposite to the first conductivity type; a channel in a middle portion and interposed between the source and drain; and a gate formed on sidewall of the semiconductor mesa and contacting the channel. | 06-04-2015 |
20150155293 | Memory Devices and Method of Fabricating Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 06-04-2015 |
20150187783 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device and a method for fabricating the semiconductor device are provided in the present disclosure. The semiconductor device includes a substrate including a first active region and a second active region divided by a shallow trench isolation (STI) region, a protective structure located on the STI region, a first semiconductor structure on the first active region, and a second semiconductor structure on the second active region of the substrate including a high-k dielectric layer and a metal gate layer over the high-k dielectric layer. The method for fabricating the semiconductor device is a process of the high-k dielectric layer deposited before the formation of the first and second semiconductor structures. | 07-02-2015 |
20150214115 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate. | 07-30-2015 |
20150228645 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor. | 08-13-2015 |
20150236030 | Split Gate Memory Device and Method of Fabricating the Same - The present disclosure relates to a split gate memory device which requires less number of processing steps than traditional baseline processes and methods of making the same. Word gate/select gate (SG) pairs are formed around a sacrificial spacer. The resulting SG structure has a distinguishable non-planar top surface. The spacer layer that covers the select gate also follows the shape of the SG top surface. A dielectric disposed above the inter-gate dielectric layer and arranged between the neighboring sidewalls of the each memory gate and select gate provides isolation between them. | 08-20-2015 |
20150263010 | Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to a method of embedding an ESF3 memory in a HKMG integrated circuit that utilizes a replacement gate technology. The ESF3 memory is formed over a recessed substrate which prevents damage of the memory control gates during the CMP process performed on the ILD layer. An asymmetric isolation zone is also formed in the transition region between the memory cell and the periphery circuit boundary. | 09-17-2015 |
20150279849 | SILICON NITRIDE (SiN) ENCAPSULATING LAYER FOR SILICON NANOCRYSTAL MEMORY STORAGE - Some embodiments relate to a memory cell with a charge-trapping layer of nanocrystals, comprising a tunneling oxide layer along a select gate, a control oxide layer formed between a control gate and the tunnel oxide layer, and a plurality of nanocrystals arranged between the tunneling and control oxide layers. An encapsulating layer isolates the nanocrystals from the control oxide layer. Contact formation to the select gate includes a two-step etch. A first etch includes a selectivity between oxide and the encapsulating layer, and etches away the control oxide layer while leaving the encapsulating layer intact. A second etch, which has an opposite selectivity of the first etch, then etches away the encapsulating layer while leaving the tunneling oxide layer intact. As a result, the control oxide layer and nanocrystals are etched away from a surface of the select gate, while leaving the tunneling oxide layer intact for contact isolation. | 10-01-2015 |
20150280004 | EMBEDDED NONVOLATILE MEMORY - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 10-01-2015 |
20150311296 | Memory Devices and Method of Forming Same - A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. | 10-29-2015 |
20150325669 | Cost-Effective Gate Replacement Process - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device. | 11-12-2015 |
20150333082 | DUAL SILICIDE FORMATION METHOD TO EMBED SPLIT GATE FLASHMEMORY IN HIGH-K METAL GATE (HKMG) TECHNOLOGY - The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a high-K metal gate (HKMG) integrated circuit that utilizes a replacement gate technology with low poly resistance and high program/erase speed. A silicide layer formed over top surfaces of the NVM device, after replacement gate process of the HKMG circuit prevents poly damage during contact formation and provides low gate resistance, thereby improving program/erase speed of the NVM device. | 11-19-2015 |
20150340493 | HK EMBODIED FLASH MEMORY AND METHODS OF FORMING THE SAME - A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device. | 11-26-2015 |
20150364482 | EMBEDDED NONVOLATILE MEMORY AND FORMING METHOD THEREOF - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 12-17-2015 |
20150364575 | SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) - Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric. | 12-17-2015 |
20160005756 | HKMG HIGH VOLTAGE CMOS FOR EMBEDDED NON-VOLATILE MEMORY - The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size. | 01-07-2016 |
20160056250 | Recessed Salicide Structure to Integrate a Flash Memory Device with a High K, Metal Gate Logic Device - Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad. | 02-25-2016 |
20160141298 | STI RECESS METHOD TO EMBED NVM MEMORY IN HKMG REPLACEMENT GATE TECHNOLOGY - The present disclosure relates to a structure and method for reducing contact over-etching and high contact resistance (Rc) on an embedded flash memory HKMG integrated circuit. In one embodiment, an STI region underlying a memory contact pad region is recessed to make the STI surface substantially co-planar with the rest of the semiconductor substrate. The recess allows formation of thicker memory contact pad structures. The thicker polysilicon on these contact pad structures prevents contact over-etching and thus reduces the Rc of contacts formed thereon. | 05-19-2016 |
Wei-Ding Wu, Zhubei City TW
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20130320459 | Semiconductor Isolation Structure with Air Gaps in Deep Trenches - A device includes a semiconductor substrate, a contact plug over the semiconductor substrate, and an Inter-Layer Dielectric (ILD) layer over the semiconductor substrate, with the contact plug being disposed in the ILD. An air gap is sealed by a portion of the ILD and the semiconductor substrate. The air gap forms a full air gap ring encircling a portion of the semiconductor substrate. | 12-05-2013 |
Wen-Che Wu, Zhubei City TW
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20130016195 | DEVICE AND METHOD FOR 3-D DISPLAY CONTROL - A control device for three dimensional display has an image processor and a timing signal generator. The image processor is used for receiving a first and a second input image signals to generate a first, a second, and a third output image signals. The first output image signal comprises part of the first input image signal. The second output image signal comprises part of the first input image signal and part of the second input image signal. The third output image signal comprises part of the second input image signal. The timing signal generator is used for generating a first lens control signal for configuring a first lens to be non-opaque when the second output image signal is displayed on a display device, and generating a second lens control signal for configuring a second lens to be non-opaque when the third output image signal is displayed on the display device. | 01-17-2013 |
20140354334 | CIRCUIT AND METHOD OF ADJUSTING SYSTEM CLOCK IN LOW VOLTAGE DETECTION, AND LOW VOLTAGE RESET CIRCUIT - The present invention discloses a circuit and a method of adjusting system clock in low voltage detection, and a low voltage reset circuit. The circuit of adjusting system clock in low voltage detection comprises: a clock generator for supplying a clock to at least one circuit in a system; and a low voltage reset circuit for generating an adjustment signal according to a detected voltage level, so that the clock generator adjusts or stops the clock supplied to the at least one circuit in the system. | 12-04-2014 |
Yi-Huang Wu, Zhubei City TW
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20130143391 | REACTED LAYER FOR IMPROVING THICKNESS UNIFORMITY OF STRAINED STRUCTURES - Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess. The improved thickness uniformity in turn improves the uniformity of device performance. | 06-06-2013 |
20130228826 | MOS Devices with Modulated Performance and Methods for Forming the Same - A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance. | 09-05-2013 |
20160027702 | MOS Devices with Modulated Performance and Methods for Forming the Same - A device includes a semiconductor substrate, a first Metal-Oxide-Semiconductor (MOS) device, and a second MOS device of a same conductivity as the first MOS device. The first MOS device includes a first gate stack over the semiconductor substrate, and a first stressor adjacent to the first gate stack and extending into the semiconductor substrate. The first stressor and the first gate stack have a first distance. The second MOS device includes a second gate stack over the semiconductor substrate, and a second stressor adjacent to the second gate stack and extending into the semiconductor substrate. The second stressor and the second gate stack have a second distance greater than the first distance. | 01-28-2016 |
Ying-Peng Wu, Zhubei City TW
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20160142791 | VIDEO BANDWIDTH ADAPTING DEVICE AND ADAPTING METHOD - Provided is a video bandwidth adapting device and adapting method. This device first sets a plurality of network transmission paths according to bit rate settings of an IP camera (IPCam), selects one from the network transmission paths to acquire a video stream provided by the IPCam, then plays the video stream in a streaming playback manner, and afterwards, when it is determined that an average delay during playing of the video stream reaches or exceeds an upper limit, selects a network transmission path corresponding to a bit rate setting whose level is lower than that of the bit rate setting of the video stream, so as to acquire a video stream with a lower-level bit rate setting through the network transmission path. | 05-19-2016 |
Ying-Yi Wu, Zhubei City TW
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20160142600 | METHOD FOR TAKING PHOTO WITH EXTENSION FLASH MODULE OF MOBILE DEVICE - A method for taking photo with an extension flash module of a mobile device is provided in the present invention. The mobile device operates in coordination with an extension flash module to achieve fill light while taking photo. The method includes the following steps: detecting a specific event before a flashable period. The flashable period starts from the time at which a last row of photo sensors begins exposure to the time at which a first row of photo sensors ends exposure. The time at which the specific event occurs is a fixed period of time compared to the flashable time. Then, triggering a flash instruction according to a flash delay time and a period from the time at which the specific event occurs to the flashable time, such that the extension flash module flashes during the flashable time. | 05-19-2016 |
Yu-Kuang Wu, Zhubei City TW
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20140203749 | MOTOR CONTROLLER HAVING MULTI-FUNCTIONAL PIN AND CONTROL METHOD THEREOF - The present invention provides a motor controller having one or more multi-functional pins. The motor controller includes a plurality of pins but does not include a dedicated pin for transmitting a clock signal and a dedicated pin for transmitting a motor specification database setting signal, wherein the clock signal and the motor specification database setting signal are for setting motor specification data. The clock signal and the motor specification database setting signal are transmitted through two of the plural pins which are multi-functional function pins shared by other functions in a normal operation mode. In a motor specification database setting mode, these multi-functional function pins are used for transmitting the clock signal and the motor specification database setting signal. In the normal operation mode, these multi-functional function pins are used for other functions. | 07-24-2014 |
Yu Shun Wu, Zhubei City TW
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20140351384 | INTERNET MULTIMEDIA PLAYBOOK SYSTEM AND METHOD THEREOF - An internet multimedia playback system and a method thereof are provided. The internet multimedia playback system includes a multimedia server, a playlist server, an internet device and an internet multimedia playback device. The multimedia server is for storing a plurality of video streams. The playlist server is for storing playlists according to different accounts. The internet device links the multimedia server and the playlist server, wherein a user can link the playlist server with a specific account thereof, and then add the internet address about the video stream that the user wants to watch, to the playlist server with the playlist form. When the internet multimedia playback device is turned on, the internet multimedia playback device links the playlist server with the specific account to acquire the playlist corresponding to the specific account, and then links to the multimedia server according to the internet address in the playlist to sequentially play the videos in the playlist. | 11-27-2014 |
Zong-Han Wu, Zhubei City TW
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20140379976 | MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD - A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module. | 12-25-2014 |