Patent application number | Description | Published |
20100114691 | MANAGING A MARKETING TEMPLATE USED IN AN E-MAIL MARKETING CAMPAIGN - Embodiments of systems, methods, and software applications, which are configured to manage marketing templates that are to be used in e-mail marketing campaigns, are described in the present disclosure. According to one embodiment, among many, a computer readable medium is configured to store instructions that are executable by a processing device. The computer readable medium includes logic adapted to enable a user to create a marketing template and logic adapted to enable the user to publish the marketing template on one or more social networks. The computer readable medium also includes logic adapted to enable the user to incorporate the marketing template into an e-mail marketing campaign. Furthermore, the computer readable medium comprises logic that is adapted to track statistics related to recipients' responses to the e-mail marketing campaign. | 05-06-2010 |
20100114991 | MANAGING THE CONTENT OF SHARED SLIDE PRESENTATIONS - Systems, methods, and software applications for managing slide presentation content are described in the present disclosure. According to one embodiment, among many, a computer readable medium is configured to store instructions that are executable by a processing device. The computer readable medium comprises logic adapted to enable a user to enter one or more search terms via a graphical user interface, the one or more search terms being used to initiate a text search of individual slides disassembled from one or more slide presentations and stored in an external database. Additional logic is adapted to display results of the text search on the graphical user interface, which displays a visual representation of a plurality of the individual slides resulting from the text search. The computer readable medium also includes logic adapted to enable a user to select one or more of the individual slides displayed on the graphical user interface. | 05-06-2010 |
Patent application number | Description | Published |
20100238937 | HIGH SPEED PACKET FIFO INPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP AND RETRANSMIT - Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a plurality of registers configured to receive N-bit portions of data in packets and a plurality of one-port memories, each having width W segmented into S portions a width W/S. A first logic module is coupled to the registers and the one-port memories and receives the N-bit portions of data in and the outputs of the registers. A second logic module coupled to the one-port memories constructs data out read from the one-port memories. In a sequence of clock cycles, the N-bit data portions are alternately transferred from the first logic module to a segment of the one-port memories, and, for each clock cycle, the second logic module constructs the data out packet with output width based on the speedup factor of m. | 09-23-2010 |
20100238938 | HIGH SPEED PACKET FIFO OUTPUT BUFFERS FOR SWITCH FABRIC WITH SPEEDUP - Described embodiments provide a first-in, first-out (FIFO) buffer for packet switching in a crossbar switch with a speedup factor of m. The FIFO buffer comprises a first logic module that receives m N-bit data portions from a switch fabric, the m N-bit data portions comprising one or more N-bit data words of one or more data packets. A plurality of one-port memories store the received data portions. Each one-port memory has a width W segmented into S portions of width W/S, where W/S is related to N. A second logic module provides one or more N-bit data words, from the one-port memories, corresponding to the received m N-bit data portions. In a sequence of clock cycles, the data portions are alternately transferred from corresponding segments of the one-port memories in a round-robin fashion, and, for each clock cycle, the second logic module constructs data out read from the one-port memories. | 09-23-2010 |
20100272117 | Buffered Crossbar Switch System - Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an N | 10-28-2010 |
20100333057 | Parametric Data-Based Process Monitoring for Adaptive Body Bias Control - Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage. | 12-30-2010 |
20110310691 | Multi-Port Memory Using Single-Port Memory Cells - A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle. | 12-22-2011 |
20120042096 | PACKET SEQUENCE NUMBER TRACKING FOR AN ANTI-REPLAY WINDOW - Described embodiments provide a network processor that includes a security sub-processor to prevent replay attacks on the network processor. A memory stores an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has N bits initialized to correspond to data packet sequence numbers in the range 1 to N. The anti-replay memory is stored in a plurality of data words. A plurality of flip-flops store word valid bits corresponding to each of the data words. A multiplexer selects the word valid bit corresponding to a data word requested by the security processor, and an AND gate performs a bitwise AND operation between the selected data word and word valid bit. When the network processor receives a data packet, the security sub-processor determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. | 02-16-2012 |
20120174216 | SECURITY PROTOCOL PROCESSING FOR ANTI-REPLAY PROTECTION - Described embodiments provide a network processor that includes a security protocol processor to prevent replay attacks on the network processor. A memory stores security associations for anti-replay operations. A pre-fetch module retrieves an anti-replay window corresponding to a data stream of the network processor. The anti-replay window has a range of sequence numbers. When the network processor receives a data packet, the security hardware accelerator determines a value of the received sequence number with respect to minimum and maximum values of a sequence number range of the anti-replay window. Depending on the value, the data packet is either received or accepted. The anti-replay window might be updated to reflect the receipt of the most recent data packet. | 07-05-2012 |
20120278615 | SECURTIY ASSOCIATION PREFETCH FOR SECURITY PROTCOL PROCESSING - Described embodiments provide a network processor that includes a security protocol processor for staged security processing of a packet having a security association (SA). An SA request module computes an address for the SA. The SA is fetched to a local memory. An SA prefetch control word (SPCW) is read from the SA in the local memory. The SPCW identifies one or more regions of the SA and the associated stages for the one or more regions. An SPCW parser generates one or more stage SPCWs (SSPCWs) from the SPCW. Each of the SSPCWs is stored in a corresponding SSPCW register. A prefetch module services each SSPCW register in accordance with a predefined algorithm. The prefetch module fetches a requested SA region and provides the requested SA region to a corresponding stage for the staged security processing of an associated portion of the packet. | 11-01-2012 |
Patent application number | Description | Published |
20080304559 | SYSTEM FOR AUTOMATIC BANDWIDTH CONTROL OF EQUALIZER ADAPTATION LOOPS - A method to reduce peak power consumption during adaptation for an IC with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops. | 12-11-2008 |
20090108925 | LOW POWER ON-CHIP GLOBAL INTERCONNECTS - An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal. | 04-30-2009 |
20110211582 | Interconnects using Self-timed Time-Division Multiplexed Bus - A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data without modification from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front. | 09-01-2011 |
20120124257 | MULTICHIP MODULE FOR COMMUNICATIONS - An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another. | 05-17-2012 |
20120248569 | INTERPOSER HAVING AN INDUCTOR - An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures. | 10-04-2012 |
20130148450 | CONTENTION-FREE MEMORY ARRANGEMENT - A memory arrangement includes a plurality of memory blocks, a first group of access ports, and a second group of access ports. Routing circuitry couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion. | 06-13-2013 |
20130214432 | STACKED DIE ASSEMBLY - Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. | 08-22-2013 |
20140254232 | INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTING MEMORY IN AN INTEGRATED CIRCUIT DEVICE - An integrated circuit device having memory is disclosed. The integrated circuit device comprises programmable resources; programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling a communication of signals with the programmable resources; a plurality of memory blocks; and dedicated interconnect elements coupled to the plurality of memory blocks, the dedicated interconnect elements enabling access to the plurality of memory blocks. A method of implementing memory in an integrated circuit device is also disclosed. | 09-11-2014 |
Patent application number | Description | Published |
20130275363 | META-DATA DRIVEN DATA INGESTION USING MAPREDUCE FRAMEWORK - A generic approach for automatically ingesting data into an HDFS (Hadoop File System) based data warehouse includes a datahub server, a generic pipelined data loading framework, and a meta-data model that, together, address data loading efficiency, data source heterogeneities, and data warehouse schema evolvement. The loading efficiency is achieved via the MapReduce scale-out solution. The meta-data model is comprised of configuration files and a catalog. The configuration file is setup per ingestion task. The catalog manages the data warehouse schema. When a scheduled data loading task is executed, the configuration files and the catalog collaboratively drive the datahub server to load the heterogeneous data to their destination schemas automatically. | 10-17-2013 |
20140279074 | DATA MANAGEMENT PLATFORM FOR DIGITAL ADVERTISING - A data management apparatus for digital advertising includes a data integration processor for collecting and storing data from providers, resolving heterogeneity of the data at schema and data levels, and performing validity checks of the data; an analytics processor for receiving validated data from the data integration processor and providing to users custom, nesting-aware, SQL-like query language and a library of data mining methods, machine learning models, and analytical user profiles (AUP); and an activation processor for encapsulating complex computations performed in real-time, segment evaluation, and online user classification using runtime user profiles (RUP). | 09-18-2014 |
Patent application number | Description | Published |
20120290671 | DYNAMIC SUPPORT OF MULTIPLE MESSAGE FORMATS - A method, system, computer system and computer program product to enable a single interface to be used to prepare and present messages in a variety of different formats. For example, the single interface can be used to prepare, receive or display messages in different languages, such as English or Japanese, which require different character sets. Furthermore, the single interface supports preparing, sending, and receiving messages in multiple text formats, such as plain text, rich text, and Multiple Internet Mail Extension (MIME) format. A message can be received in a native format, and a format for providing a response to the message can be dynamically selected. The response is provided in the dynamically-selected format. | 11-15-2012 |
20130325733 | METHOD AND SYSTEM FOR INTEGRATING AN ENTERPRISE APPLICATION WITH A SOCIAL NETWORKING APPLICATION - Disclosed is an approach for integrating one or more enterprise applications with a social networking application. Integration is provided between a CRM application and the social networking application. | 12-05-2013 |